Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T31,T32
1	0	Covered	T3,T31,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T31
1	0	Unreachable
1	1	Covered	T3,T31,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	764513387	609407413	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	764513387	3766979	0	0
GntImpliesValid_A	764513387	3766979	0	0
GrantKnown_A	764513387	609407413	0	0
IdxKnown_A	764513387	609407413	0	0
IndexIsCorrect_A	764513387	3766979	0	0
LockArbDecision_A	764513387	0	0	0
NoReadyValidNoGrant_A	764513387	0	0	0
ReadyAndValidImplyGrant_A	764513387	3766979	0	0
ReqAndReadyImplyGrant_A	764513387	3766979	0	0
ReqImpliesValid_A	764513387	3766979	0	0
ReqStaysHighUntilGranted0_M	764513387	0	0	0
RoundRobin_A	764513387	2	0	974
ValidKnown_A	764513387	609407413	0	0
gen_data_port_assertion.DataFlow_A	764513387	3766979	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	609407413	0	0
T1	34571	34489	0	0
T2	102170	88305	0	0
T3	1227204	717633	0	0
T4	933171	528607	0	0
T5	9202	9134	0	0
T6	21240	18908	0	0
T7	174268	152250	0	0
T8	1664704	998526	0	0
T9	1066	991	0	0
T10	1257658	791453	0	0
T11	314914	156752	0	0
T12	89364	44584	0	0
T13	662144	660550	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	609407413	0	0
T1	34571	34489	0	0
T2	102170	88305	0	0
T3	1227204	717633	0	0
T4	933171	528607	0	0
T5	9202	9134	0	0
T6	21240	18908	0	0
T7	174268	152250	0	0
T8	1664704	998526	0	0
T9	1066	991	0	0
T10	1257658	791453	0	0
T11	314914	156752	0	0
T12	89364	44584	0	0
T13	662144	660550	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	609407413	0	0
T1	34571	34489	0	0
T2	102170	88305	0	0
T3	1227204	717633	0	0
T4	933171	528607	0	0
T5	9202	9134	0	0
T6	21240	18908	0	0
T7	174268	152250	0	0
T8	1664704	998526	0	0
T9	1066	991	0	0
T10	1257658	791453	0	0
T11	314914	156752	0	0
T12	89364	44584	0	0
T13	662144	660550	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	2	0	974
T55	190038	1	0	1
T56	0	1	0	0
T57	52278	0	0	1
T58	2504	0	0	1
T59	226170	0	0	1
T60	120332	0	0	1
T61	110408	0	0	1
T62	87067	0	0	1
T63	1117	0	0	1
T64	1765	0	0	1
T65	104130	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	609407413	0	0
T1	34571	34489	0	0
T2	102170	88305	0	0
T3	1227204	717633	0	0
T4	933171	528607	0	0
T5	9202	9134	0	0
T6	21240	18908	0	0
T7	174268	152250	0	0
T8	1664704	998526	0	0
T9	1066	991	0	0
T10	1257658	791453	0	0
T11	314914	156752	0	0
T12	89364	44584	0	0
T13	662144	660550	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764513387	3766979	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	1227204	10633	0	0
T4	933171	10373	0	0
T5	9202	832	0	0
T6	21240	832	0	0
T7	174268	832	0	0
T8	1664704	15757	0	0
T9	1066	0	0	0
T10	1257658	11055	0	0
T11	314914	832	0	0
T12	89364	832	0	0
T13	1324288	7903	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	420468	4183	0	0
T32	0	3958	0	0
T33	0	8795	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0
T54	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T31,T32
1	0	Covered	T3,T31,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T31
1	0	Unreachable
1	1	Covered	T3,T31,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T31,T32
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T31

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153652668	29429537	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	153652668	654393	0	0
GntImpliesValid_A	153652668	654393	0	0
GrantKnown_A	153652668	29429537	0	0
IdxKnown_A	153652668	29429537	0	0
IndexIsCorrect_A	153652668	654393	0	0
LockArbDecision_A	153652668	0	0	0
NoReadyValidNoGrant_A	153652668	0	0	0
ReadyAndValidImplyGrant_A	153652668	654393	0	0
ReqAndReadyImplyGrant_A	153652668	654393	0	0
ReqImpliesValid_A	153652668	654393	0	0
ReqStaysHighUntilGranted0_M	153652668	0	0	0
RoundRobin_A	153652668	0	0	0
ValidKnown_A	153652668	29429537	0	0
gen_data_port_assertion.DataFlow_A	153652668	654393	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	29429537	0	0
T2	12957	12144	0	0
T3	505151	390672	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	29429537	0	0
T2	12957	12144	0	0
T3	505151	390672	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	29429537	0	0
T2	12957	12144	0	0
T3	505151	390672	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	29429537	0	0
T2	12957	12144	0	0
T3	505151	390672	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T31	0	53216	0	0
T32	0	92344	0	0
T33	0	260432	0	0
T34	0	63912	0	0
T35	0	56664	0	0
T36	0	50216	0	0
T37	0	9752	0	0
T39	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	654393	0	0
T3	505151	5038	0	0
T4	404057	0	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	0	0	0
T10	462505	0	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	0	0	0
T14	0	9482	0	0
T29	0	4633	0	0
T30	0	1644	0	0
T31	210234	1187	0	0
T32	0	3136	0	0
T33	0	3598	0	0
T36	0	2352	0	0
T37	0	460	0	0
T38	0	356	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153652668	122857254	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	153652668	807113	0	0
GntImpliesValid_A	153652668	807113	0	0
GrantKnown_A	153652668	122857254	0	0
IdxKnown_A	153652668	122857254	0	0
IndexIsCorrect_A	153652668	807113	0	0
LockArbDecision_A	153652668	0	0	0
NoReadyValidNoGrant_A	153652668	0	0	0
ReadyAndValidImplyGrant_A	153652668	807113	0	0
ReqAndReadyImplyGrant_A	153652668	807113	0	0
ReqImpliesValid_A	153652668	807113	0	0
ReqStaysHighUntilGranted0_M	153652668	0	0	0
RoundRobin_A	153652668	0	0	0
ValidKnown_A	153652668	122857254	0	0
gen_data_port_assertion.DataFlow_A	153652668	807113	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	122857254	0	0
T1	5304	5304	0	0
T2	12957	0	0	0
T3	505151	110132	0	0
T4	404057	403556	0	0
T6	2096	1914	0	0
T7	21589	21237	0	0
T8	664277	662386	0	0
T10	462505	458815	0	0
T11	157457	156752	0	0
T12	44682	44584	0	0
T13	0	660550	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	122857254	0	0
T1	5304	5304	0	0
T2	12957	0	0	0
T3	505151	110132	0	0
T4	404057	403556	0	0
T6	2096	1914	0	0
T7	21589	21237	0	0
T8	664277	662386	0	0
T10	462505	458815	0	0
T11	157457	156752	0	0
T12	44682	44584	0	0
T13	0	660550	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	122857254	0	0
T1	5304	5304	0	0
T2	12957	0	0	0
T3	505151	110132	0	0
T4	404057	403556	0	0
T6	2096	1914	0	0
T7	21589	21237	0	0
T8	664277	662386	0	0
T10	462505	458815	0	0
T11	157457	156752	0	0
T12	44682	44584	0	0
T13	0	660550	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	122857254	0	0
T1	5304	5304	0	0
T2	12957	0	0	0
T3	505151	110132	0	0
T4	404057	403556	0	0
T6	2096	1914	0	0
T7	21589	21237	0	0
T8	664277	662386	0	0
T10	462505	458815	0	0
T11	157457	156752	0	0
T12	44682	44584	0	0
T13	0	660550	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153652668	807113	0	0
T3	505151	516	0	0
T4	404057	5119	0	0
T6	2096	0	0	0
T7	21589	0	0	0
T8	664277	9372	0	0
T10	462505	2286	0	0
T11	157457	0	0	0
T12	44682	0	0	0
T13	662144	7903	0	0
T31	210234	2996	0	0
T32	0	822	0	0
T33	0	5197	0	0
T48	0	2966	0	0
T54	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	457208051	457120622	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	457208051	2305473	0	0
GntImpliesValid_A	457208051	2305473	0	0
GrantKnown_A	457208051	457120622	0	0
IdxKnown_A	457208051	457120622	0	0
IndexIsCorrect_A	457208051	2305473	0	0
LockArbDecision_A	457208051	0	0	0
NoReadyValidNoGrant_A	457208051	0	0	0
ReadyAndValidImplyGrant_A	457208051	2305473	0	0
ReqAndReadyImplyGrant_A	457208051	2305473	0	0
ReqImpliesValid_A	457208051	2305473	0	0
ReqStaysHighUntilGranted0_M	457208051	0	0	0
RoundRobin_A	457208051	2	0	974
ValidKnown_A	457208051	457120622	0	0
gen_data_port_assertion.DataFlow_A	457208051	2305473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2	0	974
T55	190038	1	0	1
T56	0	1	0	0
T57	52278	0	0	1
T58	2504	0	0	1
T59	226170	0	0	1
T60	120332	0	0	1
T61	110408	0	0	1
T62	87067	0	0	1
T63	1117	0	0	1
T64	1765	0	0	1
T65	104130	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	2305473	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5079	0	0
T4	125057	5254	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	832	0	0
T8	336150	6385	0	0
T9	1066	0	0	0
T10	332648	8769	0	0
T11	0	832	0	0
T12	0	832	0	0