Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3641 |
0 |
0 |
T91 |
20152 |
5 |
0 |
0 |
T92 |
29748 |
4 |
0 |
0 |
T93 |
37803 |
3 |
0 |
0 |
T94 |
5574 |
4 |
0 |
0 |
T95 |
16046 |
8 |
0 |
0 |
T96 |
6571 |
75 |
0 |
0 |
T105 |
54923 |
2 |
0 |
0 |
T112 |
110848 |
4 |
0 |
0 |
T113 |
33389 |
2 |
0 |
0 |
T114 |
66374 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
2862 |
0 |
0 |
T93 |
37803 |
24 |
0 |
0 |
T94 |
5574 |
9 |
0 |
0 |
T95 |
16046 |
23 |
0 |
0 |
T112 |
110848 |
126 |
0 |
0 |
T113 |
33389 |
32 |
0 |
0 |
T114 |
66374 |
82 |
0 |
0 |
T116 |
112165 |
659 |
0 |
0 |
T141 |
14282 |
42 |
0 |
0 |
T142 |
13660 |
46 |
0 |
0 |
T152 |
18551 |
24 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3253 |
0 |
0 |
T93 |
37803 |
37 |
0 |
0 |
T94 |
5574 |
9 |
0 |
0 |
T95 |
16046 |
26 |
0 |
0 |
T112 |
110848 |
116 |
0 |
0 |
T113 |
33389 |
43 |
0 |
0 |
T114 |
66374 |
68 |
0 |
0 |
T116 |
112165 |
667 |
0 |
0 |
T141 |
14282 |
10 |
0 |
0 |
T142 |
13660 |
52 |
0 |
0 |
T152 |
18551 |
35 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3685 |
0 |
0 |
T93 |
37803 |
86 |
0 |
0 |
T94 |
5574 |
14 |
0 |
0 |
T95 |
16046 |
31 |
0 |
0 |
T112 |
110848 |
206 |
0 |
0 |
T113 |
33389 |
97 |
0 |
0 |
T114 |
66374 |
96 |
0 |
0 |
T116 |
112165 |
655 |
0 |
0 |
T141 |
14282 |
7 |
0 |
0 |
T142 |
13660 |
47 |
0 |
0 |
T152 |
18551 |
20 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
13802 |
0 |
0 |
T93 |
37803 |
794 |
0 |
0 |
T94 |
5574 |
153 |
0 |
0 |
T95 |
16046 |
276 |
0 |
0 |
T112 |
110848 |
2091 |
0 |
0 |
T113 |
33389 |
309 |
0 |
0 |
T114 |
66374 |
1514 |
0 |
0 |
T116 |
112165 |
725 |
0 |
0 |
T141 |
14282 |
17 |
0 |
0 |
T142 |
13660 |
25 |
0 |
0 |
T152 |
18551 |
52 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
13785 |
0 |
0 |
T93 |
37803 |
809 |
0 |
0 |
T94 |
5574 |
10 |
0 |
0 |
T95 |
16046 |
143 |
0 |
0 |
T112 |
110848 |
2218 |
0 |
0 |
T113 |
33389 |
844 |
0 |
0 |
T114 |
66374 |
1151 |
0 |
0 |
T116 |
112165 |
696 |
0 |
0 |
T141 |
14282 |
23 |
0 |
0 |
T142 |
13660 |
46 |
0 |
0 |
T152 |
18551 |
51 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
12045 |
0 |
0 |
T93 |
37803 |
327 |
0 |
0 |
T94 |
5574 |
7 |
0 |
0 |
T95 |
16046 |
18 |
0 |
0 |
T112 |
110848 |
2078 |
0 |
0 |
T113 |
33389 |
653 |
0 |
0 |
T114 |
66374 |
896 |
0 |
0 |
T116 |
112165 |
715 |
0 |
0 |
T141 |
14282 |
72 |
0 |
0 |
T142 |
13660 |
46 |
0 |
0 |
T152 |
18551 |
32 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
13153 |
0 |
0 |
T93 |
37803 |
932 |
0 |
0 |
T94 |
5574 |
9 |
0 |
0 |
T95 |
16046 |
360 |
0 |
0 |
T112 |
110848 |
1707 |
0 |
0 |
T113 |
33389 |
739 |
0 |
0 |
T114 |
66374 |
809 |
0 |
0 |
T116 |
112165 |
776 |
0 |
0 |
T141 |
14282 |
23 |
0 |
0 |
T142 |
13660 |
52 |
0 |
0 |
T152 |
18551 |
56 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
14272 |
0 |
0 |
T93 |
37803 |
843 |
0 |
0 |
T94 |
5574 |
5 |
0 |
0 |
T95 |
16046 |
20 |
0 |
0 |
T112 |
110848 |
2636 |
0 |
0 |
T113 |
33389 |
432 |
0 |
0 |
T114 |
66374 |
1516 |
0 |
0 |
T116 |
112165 |
745 |
0 |
0 |
T141 |
14282 |
46 |
0 |
0 |
T142 |
13660 |
73 |
0 |
0 |
T152 |
18551 |
42 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
12757 |
0 |
0 |
T93 |
37803 |
425 |
0 |
0 |
T94 |
5574 |
6 |
0 |
0 |
T95 |
16046 |
140 |
0 |
0 |
T112 |
110848 |
2301 |
0 |
0 |
T113 |
33389 |
611 |
0 |
0 |
T114 |
66374 |
945 |
0 |
0 |
T116 |
112165 |
710 |
0 |
0 |
T141 |
14282 |
77 |
0 |
0 |
T142 |
13660 |
39 |
0 |
0 |
T152 |
18551 |
5 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
13471 |
0 |
0 |
T93 |
37803 |
624 |
0 |
0 |
T94 |
5574 |
9 |
0 |
0 |
T95 |
16046 |
284 |
0 |
0 |
T112 |
110848 |
2365 |
0 |
0 |
T113 |
33389 |
526 |
0 |
0 |
T114 |
66374 |
1527 |
0 |
0 |
T116 |
112165 |
719 |
0 |
0 |
T141 |
14282 |
50 |
0 |
0 |
T142 |
13660 |
67 |
0 |
0 |
T152 |
18551 |
39 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
14102 |
0 |
0 |
T93 |
37803 |
596 |
0 |
0 |
T94 |
5574 |
152 |
0 |
0 |
T95 |
16046 |
268 |
0 |
0 |
T112 |
110848 |
1724 |
0 |
0 |
T113 |
33389 |
676 |
0 |
0 |
T114 |
66374 |
1227 |
0 |
0 |
T116 |
112165 |
711 |
0 |
0 |
T141 |
14282 |
14 |
0 |
0 |
T142 |
13660 |
25 |
0 |
0 |
T152 |
18551 |
29 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6723 |
0 |
0 |
T93 |
37803 |
222 |
0 |
0 |
T94 |
5574 |
9 |
0 |
0 |
T95 |
16046 |
67 |
0 |
0 |
T112 |
110848 |
780 |
0 |
0 |
T113 |
33389 |
280 |
0 |
0 |
T114 |
66374 |
527 |
0 |
0 |
T116 |
112165 |
735 |
0 |
0 |
T141 |
14282 |
12 |
0 |
0 |
T142 |
13660 |
31 |
0 |
0 |
T152 |
18551 |
54 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6991 |
0 |
0 |
T93 |
37803 |
387 |
0 |
0 |
T94 |
5574 |
6 |
0 |
0 |
T95 |
16046 |
30 |
0 |
0 |
T112 |
110848 |
772 |
0 |
0 |
T113 |
33389 |
152 |
0 |
0 |
T114 |
66374 |
556 |
0 |
0 |
T116 |
112165 |
674 |
0 |
0 |
T141 |
14282 |
51 |
0 |
0 |
T142 |
13660 |
50 |
0 |
0 |
T152 |
18551 |
68 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7068 |
0 |
0 |
T93 |
37803 |
453 |
0 |
0 |
T94 |
5574 |
51 |
0 |
0 |
T95 |
16046 |
108 |
0 |
0 |
T112 |
110848 |
613 |
0 |
0 |
T113 |
33389 |
171 |
0 |
0 |
T114 |
66374 |
474 |
0 |
0 |
T116 |
112165 |
715 |
0 |
0 |
T141 |
14282 |
29 |
0 |
0 |
T142 |
13660 |
79 |
0 |
0 |
T152 |
18551 |
37 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7243 |
0 |
0 |
T93 |
37803 |
322 |
0 |
0 |
T94 |
5574 |
49 |
0 |
0 |
T95 |
16046 |
106 |
0 |
0 |
T112 |
110848 |
634 |
0 |
0 |
T113 |
33389 |
227 |
0 |
0 |
T114 |
66374 |
732 |
0 |
0 |
T116 |
112165 |
727 |
0 |
0 |
T141 |
14282 |
37 |
0 |
0 |
T142 |
13660 |
31 |
0 |
0 |
T152 |
18551 |
24 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7122 |
0 |
0 |
T93 |
37803 |
180 |
0 |
0 |
T94 |
5574 |
36 |
0 |
0 |
T95 |
16046 |
149 |
0 |
0 |
T112 |
110848 |
711 |
0 |
0 |
T113 |
33389 |
159 |
0 |
0 |
T114 |
66374 |
554 |
0 |
0 |
T116 |
112165 |
689 |
0 |
0 |
T141 |
14282 |
25 |
0 |
0 |
T142 |
13660 |
50 |
0 |
0 |
T152 |
18551 |
36 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6869 |
0 |
0 |
T93 |
37803 |
360 |
0 |
0 |
T95 |
16046 |
59 |
0 |
0 |
T112 |
110848 |
753 |
0 |
0 |
T113 |
33389 |
156 |
0 |
0 |
T114 |
66374 |
475 |
0 |
0 |
T116 |
112165 |
718 |
0 |
0 |
T141 |
14282 |
30 |
0 |
0 |
T142 |
13660 |
10 |
0 |
0 |
T152 |
18551 |
20 |
0 |
0 |
T153 |
65876 |
522 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7081 |
0 |
0 |
T93 |
37803 |
269 |
0 |
0 |
T94 |
5574 |
8 |
0 |
0 |
T95 |
16046 |
126 |
0 |
0 |
T112 |
110848 |
939 |
0 |
0 |
T113 |
33389 |
213 |
0 |
0 |
T114 |
66374 |
604 |
0 |
0 |
T116 |
112165 |
747 |
0 |
0 |
T141 |
14282 |
24 |
0 |
0 |
T142 |
13660 |
39 |
0 |
0 |
T152 |
18551 |
36 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7415 |
0 |
0 |
T93 |
37803 |
321 |
0 |
0 |
T94 |
5574 |
10 |
0 |
0 |
T95 |
16046 |
103 |
0 |
0 |
T112 |
110848 |
928 |
0 |
0 |
T113 |
33389 |
334 |
0 |
0 |
T114 |
66374 |
587 |
0 |
0 |
T116 |
112165 |
665 |
0 |
0 |
T141 |
14282 |
36 |
0 |
0 |
T142 |
13660 |
83 |
0 |
0 |
T152 |
18551 |
48 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7050 |
0 |
0 |
T93 |
37803 |
312 |
0 |
0 |
T94 |
5574 |
51 |
0 |
0 |
T95 |
16046 |
73 |
0 |
0 |
T112 |
110848 |
786 |
0 |
0 |
T113 |
33389 |
368 |
0 |
0 |
T114 |
66374 |
387 |
0 |
0 |
T116 |
112165 |
689 |
0 |
0 |
T141 |
14282 |
9 |
0 |
0 |
T142 |
13660 |
54 |
0 |
0 |
T152 |
18551 |
47 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
8266 |
0 |
0 |
T93 |
37803 |
241 |
0 |
0 |
T94 |
5574 |
62 |
0 |
0 |
T95 |
16046 |
112 |
0 |
0 |
T112 |
110848 |
1300 |
0 |
0 |
T113 |
33389 |
384 |
0 |
0 |
T114 |
66374 |
550 |
0 |
0 |
T116 |
112165 |
760 |
0 |
0 |
T141 |
14282 |
44 |
0 |
0 |
T142 |
13660 |
54 |
0 |
0 |
T152 |
18551 |
18 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7089 |
0 |
0 |
T93 |
37803 |
210 |
0 |
0 |
T94 |
5574 |
56 |
0 |
0 |
T95 |
16046 |
62 |
0 |
0 |
T112 |
110848 |
876 |
0 |
0 |
T113 |
33389 |
369 |
0 |
0 |
T114 |
66374 |
622 |
0 |
0 |
T116 |
112165 |
684 |
0 |
0 |
T141 |
14282 |
38 |
0 |
0 |
T142 |
13660 |
69 |
0 |
0 |
T152 |
18551 |
73 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6619 |
0 |
0 |
T93 |
37803 |
140 |
0 |
0 |
T94 |
5574 |
3 |
0 |
0 |
T95 |
16046 |
104 |
0 |
0 |
T112 |
110848 |
679 |
0 |
0 |
T113 |
33389 |
245 |
0 |
0 |
T114 |
66374 |
712 |
0 |
0 |
T116 |
112165 |
703 |
0 |
0 |
T141 |
14282 |
30 |
0 |
0 |
T142 |
13660 |
73 |
0 |
0 |
T152 |
18551 |
16 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7545 |
0 |
0 |
T93 |
37803 |
238 |
0 |
0 |
T94 |
5574 |
49 |
0 |
0 |
T95 |
16046 |
115 |
0 |
0 |
T112 |
110848 |
851 |
0 |
0 |
T113 |
33389 |
249 |
0 |
0 |
T114 |
66374 |
669 |
0 |
0 |
T116 |
112165 |
679 |
0 |
0 |
T141 |
14282 |
25 |
0 |
0 |
T142 |
13660 |
21 |
0 |
0 |
T152 |
18551 |
29 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6742 |
0 |
0 |
T93 |
37803 |
262 |
0 |
0 |
T94 |
5574 |
12 |
0 |
0 |
T95 |
16046 |
105 |
0 |
0 |
T112 |
110848 |
952 |
0 |
0 |
T113 |
33389 |
324 |
0 |
0 |
T114 |
66374 |
375 |
0 |
0 |
T116 |
112165 |
633 |
0 |
0 |
T141 |
14282 |
39 |
0 |
0 |
T142 |
13660 |
30 |
0 |
0 |
T152 |
18551 |
21 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7269 |
0 |
0 |
T93 |
37803 |
292 |
0 |
0 |
T94 |
5574 |
8 |
0 |
0 |
T95 |
16046 |
116 |
0 |
0 |
T112 |
110848 |
911 |
0 |
0 |
T113 |
33389 |
348 |
0 |
0 |
T114 |
66374 |
581 |
0 |
0 |
T116 |
112165 |
634 |
0 |
0 |
T141 |
14282 |
64 |
0 |
0 |
T142 |
13660 |
13 |
0 |
0 |
T152 |
18551 |
28 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7184 |
0 |
0 |
T93 |
37803 |
291 |
0 |
0 |
T94 |
5574 |
79 |
0 |
0 |
T95 |
16046 |
93 |
0 |
0 |
T112 |
110848 |
663 |
0 |
0 |
T113 |
33389 |
296 |
0 |
0 |
T114 |
66374 |
568 |
0 |
0 |
T116 |
112165 |
705 |
0 |
0 |
T141 |
14282 |
77 |
0 |
0 |
T142 |
13660 |
14 |
0 |
0 |
T152 |
18551 |
26 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6775 |
0 |
0 |
T93 |
37803 |
288 |
0 |
0 |
T94 |
5574 |
1 |
0 |
0 |
T95 |
16046 |
71 |
0 |
0 |
T112 |
110848 |
808 |
0 |
0 |
T113 |
33389 |
317 |
0 |
0 |
T114 |
66374 |
429 |
0 |
0 |
T116 |
112165 |
732 |
0 |
0 |
T141 |
14282 |
67 |
0 |
0 |
T142 |
13660 |
44 |
0 |
0 |
T152 |
18551 |
12 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6672 |
0 |
0 |
T93 |
37803 |
307 |
0 |
0 |
T94 |
5574 |
62 |
0 |
0 |
T95 |
16046 |
72 |
0 |
0 |
T112 |
110848 |
837 |
0 |
0 |
T113 |
33389 |
194 |
0 |
0 |
T114 |
66374 |
575 |
0 |
0 |
T116 |
112165 |
704 |
0 |
0 |
T141 |
14282 |
14 |
0 |
0 |
T142 |
13660 |
9 |
0 |
0 |
T152 |
18551 |
16 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6718 |
0 |
0 |
T93 |
37803 |
269 |
0 |
0 |
T94 |
5574 |
41 |
0 |
0 |
T95 |
16046 |
119 |
0 |
0 |
T112 |
110848 |
471 |
0 |
0 |
T113 |
33389 |
304 |
0 |
0 |
T114 |
66374 |
423 |
0 |
0 |
T116 |
112165 |
727 |
0 |
0 |
T141 |
14282 |
74 |
0 |
0 |
T142 |
13660 |
32 |
0 |
0 |
T152 |
18551 |
32 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6949 |
0 |
0 |
T93 |
37803 |
307 |
0 |
0 |
T94 |
5574 |
65 |
0 |
0 |
T95 |
16046 |
28 |
0 |
0 |
T112 |
110848 |
458 |
0 |
0 |
T113 |
33389 |
192 |
0 |
0 |
T114 |
66374 |
579 |
0 |
0 |
T116 |
112165 |
733 |
0 |
0 |
T141 |
14282 |
73 |
0 |
0 |
T142 |
13660 |
37 |
0 |
0 |
T152 |
18551 |
13 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6944 |
0 |
0 |
T93 |
37803 |
373 |
0 |
0 |
T94 |
5574 |
51 |
0 |
0 |
T95 |
16046 |
60 |
0 |
0 |
T112 |
110848 |
641 |
0 |
0 |
T113 |
33389 |
333 |
0 |
0 |
T114 |
66374 |
477 |
0 |
0 |
T116 |
112165 |
724 |
0 |
0 |
T141 |
14282 |
70 |
0 |
0 |
T142 |
13660 |
76 |
0 |
0 |
T152 |
18551 |
25 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6905 |
0 |
0 |
T93 |
37803 |
157 |
0 |
0 |
T94 |
5574 |
58 |
0 |
0 |
T95 |
16046 |
53 |
0 |
0 |
T112 |
110848 |
638 |
0 |
0 |
T113 |
33389 |
346 |
0 |
0 |
T114 |
66374 |
531 |
0 |
0 |
T116 |
112165 |
686 |
0 |
0 |
T141 |
14282 |
48 |
0 |
0 |
T142 |
13660 |
85 |
0 |
0 |
T152 |
18551 |
31 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7086 |
0 |
0 |
T93 |
37803 |
243 |
0 |
0 |
T94 |
5574 |
53 |
0 |
0 |
T95 |
16046 |
65 |
0 |
0 |
T112 |
110848 |
880 |
0 |
0 |
T113 |
33389 |
407 |
0 |
0 |
T114 |
66374 |
429 |
0 |
0 |
T116 |
112165 |
696 |
0 |
0 |
T141 |
14282 |
22 |
0 |
0 |
T142 |
13660 |
47 |
0 |
0 |
T152 |
18551 |
42 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
7578 |
0 |
0 |
T93 |
37803 |
314 |
0 |
0 |
T94 |
5574 |
3 |
0 |
0 |
T95 |
16046 |
128 |
0 |
0 |
T112 |
110848 |
978 |
0 |
0 |
T113 |
33389 |
346 |
0 |
0 |
T114 |
66374 |
581 |
0 |
0 |
T116 |
112165 |
779 |
0 |
0 |
T141 |
14282 |
41 |
0 |
0 |
T142 |
13660 |
51 |
0 |
0 |
T152 |
18551 |
25 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3323 |
0 |
0 |
T93 |
37803 |
33 |
0 |
0 |
T94 |
5574 |
7 |
0 |
0 |
T95 |
16046 |
25 |
0 |
0 |
T112 |
110848 |
143 |
0 |
0 |
T113 |
33389 |
57 |
0 |
0 |
T114 |
66374 |
115 |
0 |
0 |
T116 |
112165 |
665 |
0 |
0 |
T141 |
14282 |
38 |
0 |
0 |
T142 |
13660 |
64 |
0 |
0 |
T152 |
18551 |
8 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3496 |
0 |
0 |
T93 |
37803 |
47 |
0 |
0 |
T94 |
5574 |
11 |
0 |
0 |
T95 |
16046 |
34 |
0 |
0 |
T112 |
110848 |
172 |
0 |
0 |
T113 |
33389 |
50 |
0 |
0 |
T114 |
66374 |
136 |
0 |
0 |
T116 |
112165 |
732 |
0 |
0 |
T141 |
14282 |
48 |
0 |
0 |
T142 |
13660 |
20 |
0 |
0 |
T152 |
18551 |
35 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3455 |
0 |
0 |
T93 |
37803 |
50 |
0 |
0 |
T94 |
5574 |
1 |
0 |
0 |
T95 |
16046 |
20 |
0 |
0 |
T112 |
110848 |
161 |
0 |
0 |
T113 |
33389 |
93 |
0 |
0 |
T114 |
66374 |
134 |
0 |
0 |
T116 |
112165 |
639 |
0 |
0 |
T141 |
14282 |
24 |
0 |
0 |
T142 |
13660 |
46 |
0 |
0 |
T152 |
18551 |
37 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3612 |
0 |
0 |
T93 |
37803 |
57 |
0 |
0 |
T94 |
5574 |
5 |
0 |
0 |
T95 |
16046 |
29 |
0 |
0 |
T112 |
110848 |
165 |
0 |
0 |
T113 |
33389 |
54 |
0 |
0 |
T114 |
66374 |
102 |
0 |
0 |
T116 |
112165 |
731 |
0 |
0 |
T141 |
14282 |
76 |
0 |
0 |
T142 |
13660 |
21 |
0 |
0 |
T152 |
18551 |
63 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
4246 |
0 |
0 |
T93 |
37803 |
77 |
0 |
0 |
T94 |
5574 |
2 |
0 |
0 |
T95 |
16046 |
20 |
0 |
0 |
T112 |
110848 |
282 |
0 |
0 |
T113 |
33389 |
94 |
0 |
0 |
T114 |
66374 |
244 |
0 |
0 |
T116 |
112165 |
755 |
0 |
0 |
T141 |
14282 |
6 |
0 |
0 |
T142 |
13660 |
49 |
0 |
0 |
T152 |
18551 |
39 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
6368 |
0 |
0 |
T16 |
138401 |
50 |
0 |
0 |
T18 |
0 |
17 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T86 |
251745 |
0 |
0 |
0 |
T138 |
0 |
24 |
0 |
0 |
T145 |
248470 |
0 |
0 |
0 |
T146 |
36266 |
0 |
0 |
0 |
T154 |
0 |
33 |
0 |
0 |
T155 |
0 |
51 |
0 |
0 |
T156 |
0 |
12 |
0 |
0 |
T157 |
0 |
44 |
0 |
0 |
T158 |
0 |
18 |
0 |
0 |
T159 |
0 |
27 |
0 |
0 |
T160 |
343211 |
0 |
0 |
0 |
T161 |
36835 |
0 |
0 |
0 |
T162 |
14092 |
0 |
0 |
0 |
T163 |
999 |
0 |
0 |
0 |
T164 |
1288 |
0 |
0 |
0 |
T165 |
1334 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3398 |
0 |
0 |
T93 |
37803 |
57 |
0 |
0 |
T94 |
5574 |
2 |
0 |
0 |
T95 |
16046 |
35 |
0 |
0 |
T112 |
110848 |
155 |
0 |
0 |
T113 |
33389 |
40 |
0 |
0 |
T114 |
66374 |
108 |
0 |
0 |
T116 |
112165 |
712 |
0 |
0 |
T141 |
14282 |
68 |
0 |
0 |
T142 |
13660 |
38 |
0 |
0 |
T152 |
18551 |
21 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3395 |
0 |
0 |
T93 |
37803 |
47 |
0 |
0 |
T94 |
5574 |
2 |
0 |
0 |
T95 |
16046 |
16 |
0 |
0 |
T112 |
110848 |
140 |
0 |
0 |
T113 |
33389 |
77 |
0 |
0 |
T114 |
66374 |
137 |
0 |
0 |
T116 |
112165 |
683 |
0 |
0 |
T141 |
14282 |
47 |
0 |
0 |
T142 |
13660 |
52 |
0 |
0 |
T152 |
18551 |
25 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3037 |
0 |
0 |
T93 |
37803 |
37 |
0 |
0 |
T94 |
5574 |
8 |
0 |
0 |
T95 |
16046 |
17 |
0 |
0 |
T112 |
110848 |
107 |
0 |
0 |
T113 |
33389 |
43 |
0 |
0 |
T114 |
66374 |
86 |
0 |
0 |
T116 |
112165 |
739 |
0 |
0 |
T141 |
14282 |
46 |
0 |
0 |
T142 |
13660 |
34 |
0 |
0 |
T152 |
18551 |
38 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3260 |
0 |
0 |
T93 |
37803 |
33 |
0 |
0 |
T94 |
5574 |
5 |
0 |
0 |
T95 |
16046 |
18 |
0 |
0 |
T112 |
110848 |
122 |
0 |
0 |
T113 |
33389 |
46 |
0 |
0 |
T114 |
66374 |
93 |
0 |
0 |
T116 |
112165 |
730 |
0 |
0 |
T141 |
14282 |
48 |
0 |
0 |
T142 |
13660 |
75 |
0 |
0 |
T152 |
18551 |
53 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3108 |
0 |
0 |
T93 |
37803 |
28 |
0 |
0 |
T94 |
5574 |
3 |
0 |
0 |
T95 |
16046 |
19 |
0 |
0 |
T112 |
110848 |
140 |
0 |
0 |
T113 |
33389 |
21 |
0 |
0 |
T114 |
66374 |
63 |
0 |
0 |
T116 |
112165 |
727 |
0 |
0 |
T141 |
14282 |
53 |
0 |
0 |
T142 |
13660 |
28 |
0 |
0 |
T152 |
18551 |
30 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3148 |
0 |
0 |
T93 |
37803 |
44 |
0 |
0 |
T94 |
5574 |
6 |
0 |
0 |
T95 |
16046 |
29 |
0 |
0 |
T112 |
110848 |
151 |
0 |
0 |
T113 |
33389 |
46 |
0 |
0 |
T114 |
66374 |
99 |
0 |
0 |
T116 |
112165 |
666 |
0 |
0 |
T141 |
14282 |
59 |
0 |
0 |
T142 |
13660 |
45 |
0 |
0 |
T152 |
18551 |
37 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
4046 |
0 |
0 |
T93 |
37803 |
64 |
0 |
0 |
T94 |
5574 |
22 |
0 |
0 |
T95 |
16046 |
28 |
0 |
0 |
T112 |
110848 |
370 |
0 |
0 |
T113 |
33389 |
64 |
0 |
0 |
T114 |
66374 |
184 |
0 |
0 |
T116 |
112165 |
741 |
0 |
0 |
T141 |
14282 |
21 |
0 |
0 |
T142 |
13660 |
71 |
0 |
0 |
T152 |
18551 |
23 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3027 |
0 |
0 |
T93 |
37803 |
30 |
0 |
0 |
T94 |
5574 |
6 |
0 |
0 |
T95 |
16046 |
20 |
0 |
0 |
T112 |
110848 |
130 |
0 |
0 |
T113 |
33389 |
39 |
0 |
0 |
T114 |
66374 |
66 |
0 |
0 |
T116 |
112165 |
687 |
0 |
0 |
T141 |
14282 |
18 |
0 |
0 |
T142 |
13660 |
29 |
0 |
0 |
T152 |
18551 |
54 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
4506 |
0 |
0 |
T93 |
37803 |
108 |
0 |
0 |
T94 |
5574 |
8 |
0 |
0 |
T95 |
16046 |
35 |
0 |
0 |
T112 |
110848 |
290 |
0 |
0 |
T113 |
33389 |
140 |
0 |
0 |
T114 |
66374 |
231 |
0 |
0 |
T116 |
112165 |
750 |
0 |
0 |
T141 |
14282 |
73 |
0 |
0 |
T142 |
13660 |
39 |
0 |
0 |
T152 |
18551 |
28 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3297 |
0 |
0 |
T93 |
37803 |
39 |
0 |
0 |
T94 |
5574 |
15 |
0 |
0 |
T95 |
16046 |
24 |
0 |
0 |
T112 |
110848 |
157 |
0 |
0 |
T113 |
33389 |
58 |
0 |
0 |
T114 |
66374 |
128 |
0 |
0 |
T116 |
112165 |
681 |
0 |
0 |
T141 |
14282 |
39 |
0 |
0 |
T142 |
13660 |
52 |
0 |
0 |
T152 |
18551 |
65 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3236 |
0 |
0 |
T93 |
37803 |
36 |
0 |
0 |
T94 |
5574 |
14 |
0 |
0 |
T95 |
16046 |
38 |
0 |
0 |
T112 |
110848 |
120 |
0 |
0 |
T113 |
33389 |
34 |
0 |
0 |
T114 |
66374 |
87 |
0 |
0 |
T116 |
112165 |
664 |
0 |
0 |
T141 |
14282 |
47 |
0 |
0 |
T142 |
13660 |
58 |
0 |
0 |
T152 |
18551 |
26 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3125 |
0 |
0 |
T93 |
37803 |
50 |
0 |
0 |
T94 |
5574 |
8 |
0 |
0 |
T95 |
16046 |
23 |
0 |
0 |
T112 |
110848 |
91 |
0 |
0 |
T113 |
33389 |
39 |
0 |
0 |
T114 |
66374 |
85 |
0 |
0 |
T116 |
112165 |
716 |
0 |
0 |
T141 |
14282 |
32 |
0 |
0 |
T142 |
13660 |
16 |
0 |
0 |
T152 |
18551 |
16 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3192 |
0 |
0 |
T93 |
37803 |
34 |
0 |
0 |
T94 |
5574 |
12 |
0 |
0 |
T95 |
16046 |
26 |
0 |
0 |
T112 |
110848 |
110 |
0 |
0 |
T113 |
33389 |
38 |
0 |
0 |
T114 |
66374 |
100 |
0 |
0 |
T116 |
112165 |
719 |
0 |
0 |
T141 |
14282 |
92 |
0 |
0 |
T142 |
13660 |
65 |
0 |
0 |
T152 |
18551 |
18 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3098 |
0 |
0 |
T93 |
37803 |
39 |
0 |
0 |
T94 |
5574 |
3 |
0 |
0 |
T95 |
16046 |
23 |
0 |
0 |
T112 |
110848 |
121 |
0 |
0 |
T113 |
33389 |
39 |
0 |
0 |
T114 |
66374 |
70 |
0 |
0 |
T116 |
112165 |
709 |
0 |
0 |
T141 |
14282 |
49 |
0 |
0 |
T142 |
13660 |
32 |
0 |
0 |
T152 |
18551 |
54 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3142 |
0 |
0 |
T93 |
37803 |
17 |
0 |
0 |
T94 |
5574 |
5 |
0 |
0 |
T95 |
16046 |
24 |
0 |
0 |
T112 |
110848 |
133 |
0 |
0 |
T113 |
33389 |
55 |
0 |
0 |
T114 |
66374 |
69 |
0 |
0 |
T116 |
112165 |
684 |
0 |
0 |
T141 |
14282 |
36 |
0 |
0 |
T142 |
13660 |
78 |
0 |
0 |
T152 |
18551 |
44 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459927526 |
3319 |
0 |
0 |
T93 |
37803 |
43 |
0 |
0 |
T94 |
5574 |
14 |
0 |
0 |
T95 |
16046 |
18 |
0 |
0 |
T112 |
110848 |
92 |
0 |
0 |
T113 |
33389 |
40 |
0 |
0 |
T114 |
66374 |
87 |
0 |
0 |
T116 |
112165 |
737 |
0 |
0 |
T141 |
14282 |
27 |
0 |
0 |
T142 |
13660 |
74 |
0 |
0 |
T152 |
18551 |
58 |
0 |
0 |