Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3334460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4047490

1

T1

142

T2

962

T3

1615

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4147601	1			T1	990		T2	150		T3	1400
values[0x0]	1615839	1			T1	59		T2	441		T3	437
values[0x1]	1618510	1			T1	67		T2	443		T3	473

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2382233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4999717

1

T1

474

T2

979

T3

1764

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28505	1			T1	8		T2	10		T3	2
valid_sources[0x01]	29059	1			T1	4		T2	8		T3	10
valid_sources[0x02]	27193	1			T1	1		T2	4		T3	6
valid_sources[0x03]	25708	1			T1	2		T2	4		T3	4
valid_sources[0x04]	27232	1			T1	12		T2	6		T3	13
valid_sources[0x05]	26569	1			T1	2		T2	2		T3	13
valid_sources[0x06]	30589	1			T1	3		T2	10		T3	13
valid_sources[0x07]	27440	1			T1	2		T2	1		T3	7
valid_sources[0x08]	25647	1			T1	14		T2	10		T3	2
valid_sources[0x09]	27509	1			T1	7		T2	5		T3	7
valid_sources[0x0a]	28085	1			T1	3		T2	2		T3	1
valid_sources[0x0b]	27223	1			T1	6		T2	3		T3	12
valid_sources[0x0c]	27775	1			T1	6		T2	3		T3	6
valid_sources[0x0d]	32280	1			T1	4		T2	1		T3	15
valid_sources[0x0e]	27759	1			T1	2		T2	2		T3	5
valid_sources[0x0f]	27570	1			T1	10		T2	7		T3	11
valid_sources[0x10]	26354	1			T2	10		T3	9		T5	209
valid_sources[0x11]	26727	1			T1	2		T2	6		T3	4
valid_sources[0x12]	44895	1			T1	8		T2	6		T3	14
valid_sources[0x13]	26988	1			T1	7		T2	1		T3	3
valid_sources[0x14]	29647	1			T1	4		T3	8		T5	108
valid_sources[0x15]	30031	1			T1	7		T2	5		T3	12
valid_sources[0x16]	27256	1			T1	7		T2	1		T3	7
valid_sources[0x17]	26363	1			T1	1		T2	1		T3	4
valid_sources[0x18]	30120	1			T1	4		T2	1		T3	18
valid_sources[0x19]	32782	1			T1	5		T2	2		T3	14
valid_sources[0x1a]	28328	1			T1	1		T3	7		T5	149
valid_sources[0x1b]	30651	1			T1	3		T2	7		T3	4
valid_sources[0x1c]	27399	1			T1	6		T2	3		T3	13
valid_sources[0x1d]	39150	1			T1	14		T3	11		T5	126
valid_sources[0x1e]	25587	1			T1	6		T2	2		T3	10
valid_sources[0x1f]	28168	1			T1	11		T2	4		T3	6
valid_sources[0x20]	32133	1			T1	1		T3	6		T5	218
valid_sources[0x21]	31388	1			T1	3		T2	9		T3	14
valid_sources[0x22]	25089	1			T1	5		T2	4		T3	13
valid_sources[0x23]	28189	1			T1	5		T2	8		T3	5
valid_sources[0x24]	31819	1			T1	2		T2	6		T3	19
valid_sources[0x25]	25630	1			T1	7		T2	4		T3	13
valid_sources[0x26]	25587	1			T1	2		T2	5		T3	13
valid_sources[0x27]	26033	1			T1	1		T2	5		T3	6
valid_sources[0x28]	25131	1			T1	1		T2	11		T3	6
valid_sources[0x29]	26052	1			T1	5		T3	18		T5	146
valid_sources[0x2a]	29202	1			T2	2		T3	15		T5	77
valid_sources[0x2b]	27216	1			T1	10		T2	5		T3	12
valid_sources[0x2c]	27340	1			T1	6		T2	7		T3	9
valid_sources[0x2d]	25482	1			T1	2		T2	4		T3	9
valid_sources[0x2e]	26881	1			T1	6		T2	11		T3	10
valid_sources[0x2f]	28561	1			T3	4		T5	21		T8	42
valid_sources[0x30]	27895	1			T1	4		T3	6		T5	17
valid_sources[0x31]	29331	1			T1	6		T2	8		T3	11
valid_sources[0x32]	26834	1			T2	2		T3	8		T5	82
valid_sources[0x33]	24523	1			T1	9		T2	3		T3	12
valid_sources[0x34]	28025	1			T1	2		T2	4		T3	9
valid_sources[0x35]	27590	1			T1	4		T2	4		T3	4
valid_sources[0x36]	25790	1			T1	2		T2	11		T3	7
valid_sources[0x37]	31090	1			T1	8		T2	10		T3	9
valid_sources[0x38]	27820	1			T1	1		T2	4		T3	17
valid_sources[0x39]	28794	1			T1	9		T2	4		T3	11
valid_sources[0x3a]	29438	1			T1	3		T2	4		T3	10
valid_sources[0x3b]	27624	1			T1	2		T2	12		T3	9
valid_sources[0x3c]	25498	1			T2	1		T3	6		T5	502
valid_sources[0x3d]	27226	1			T1	1		T2	12		T3	6
valid_sources[0x3e]	25352	1			T1	5		T2	6		T3	4
valid_sources[0x3f]	26817	1			T1	8		T2	3		T3	6
valid_sources[0x40]	26020	1			T1	3		T2	5		T3	5
valid_sources[0x41]	29571	1			T1	10		T3	12		T5	471
valid_sources[0x42]	26697	1			T1	5		T3	14		T5	161
valid_sources[0x43]	27819	1			T1	5		T2	2		T3	6
valid_sources[0x44]	28126	1			T1	3		T2	6		T3	9
valid_sources[0x45]	29927	1			T2	9		T3	13		T5	606
valid_sources[0x46]	28881	1			T1	5		T2	5		T3	3
valid_sources[0x47]	27942	1			T1	4		T2	2		T3	8
valid_sources[0x48]	29889	1			T1	5		T2	1		T3	14
valid_sources[0x49]	27286	1			T1	3		T2	2		T3	9
valid_sources[0x4a]	27992	1			T1	2		T2	4		T3	7
valid_sources[0x4b]	30021	1			T1	5		T2	3		T3	9
valid_sources[0x4c]	26558	1			T1	2		T2	4		T3	13
valid_sources[0x4d]	26275	1			T1	3		T2	5		T3	13
valid_sources[0x4e]	34062	1			T1	3		T2	1		T3	8
valid_sources[0x4f]	28580	1			T1	1		T2	8		T3	8
valid_sources[0x50]	29328	1			T1	8		T2	2		T3	5
valid_sources[0x51]	28058	1			T1	2		T2	1		T3	12
valid_sources[0x52]	74472	1			T1	5		T2	2		T3	6
valid_sources[0x53]	24683	1			T1	6		T2	6		T3	3
valid_sources[0x54]	27598	1			T1	6		T2	3		T3	5
valid_sources[0x55]	28496	1			T1	4		T2	3		T3	8
valid_sources[0x56]	27805	1			T1	11		T3	5		T5	230
valid_sources[0x57]	36271	1			T1	7		T2	6		T3	2
valid_sources[0x58]	27278	1			T1	6		T2	6		T3	11
valid_sources[0x59]	27021	1			T2	5		T3	2		T5	123
valid_sources[0x5a]	27881	1			T1	4		T2	3		T3	12
valid_sources[0x5b]	28884	1			T1	3		T2	6		T3	9
valid_sources[0x5c]	32698	1			T1	1		T2	2		T3	6
valid_sources[0x5d]	27385	1			T1	7		T2	1		T3	12
valid_sources[0x5e]	29660	1			T1	2		T2	12		T3	6
valid_sources[0x5f]	26563	1			T1	3		T2	3		T3	12
valid_sources[0x60]	28563	1			T1	4		T2	3		T3	18
valid_sources[0x61]	28578	1			T1	2		T2	1		T3	11
valid_sources[0x62]	25723	1			T1	10		T3	3		T5	263
valid_sources[0x63]	26405	1			T1	3		T2	6		T3	2
valid_sources[0x64]	28144	1			T1	2		T2	12		T3	23
valid_sources[0x65]	27558	1			T1	6		T2	3		T3	8
valid_sources[0x66]	30551	1			T1	4		T2	2		T3	7
valid_sources[0x67]	28729	1			T1	4		T2	5		T3	7
valid_sources[0x68]	41671	1			T2	3		T3	10		T5	259
valid_sources[0x69]	30954	1			T1	8		T2	2		T3	12
valid_sources[0x6a]	29919	1			T1	14		T2	9		T3	6
valid_sources[0x6b]	25168	1			T1	11		T2	5		T3	7
valid_sources[0x6c]	25208	1			T1	2		T2	6		T3	7
valid_sources[0x6d]	28087	1			T1	4		T2	4		T3	6
valid_sources[0x6e]	31236	1			T1	7		T2	3		T3	7
valid_sources[0x6f]	26805	1			T1	3		T3	8		T5	15
valid_sources[0x70]	26136	1			T1	1		T2	1		T3	9
valid_sources[0x71]	29441	1			T1	5		T2	2		T3	10
valid_sources[0x72]	27268	1			T1	3		T3	11		T5	203
valid_sources[0x73]	27584	1			T1	6		T2	6		T3	13
valid_sources[0x74]	29393	1			T1	2		T2	4		T3	7
valid_sources[0x75]	28207	1			T2	5		T3	13		T5	116
valid_sources[0x76]	26847	1			T1	1		T2	3		T3	9
valid_sources[0x77]	26190	1			T1	12		T2	3		T3	6
valid_sources[0x78]	24916	1			T1	15		T2	4		T3	15
valid_sources[0x79]	25898	1			T1	2		T2	3		T3	5
valid_sources[0x7a]	29210	1			T1	4		T2	5		T3	14
valid_sources[0x7b]	31274	1			T1	8		T2	10		T3	18
valid_sources[0x7c]	25642	1			T1	4		T2	5		T3	9
valid_sources[0x7d]	25684	1			T1	7		T2	5		T3	8
valid_sources[0x7e]	27927	1			T1	1		T2	7		T3	7
valid_sources[0x7f]	29429	1			T1	4		T2	5		T3	11
valid_sources[0x80]	27749	1			T1	3		T2	1		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1108061

1

T1

52

T2

81

T3

712

values[0x0]

all_enables

biggest_size

1479684

1

T1

49

T2

439

T3

436

values[0x1]

all_enables

biggest_size

1459745

1

T1

41

T2

442

T3

467