Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3356069

1

T1

974

T2

72

T3

695

full_word

4046821

1

T1

142

T2

962

T3

1615

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7402420	1			T1	1116		T2	1034		T3	2310
auto[TlIntgErrCmd]	173	1			T102	6		T103	4		T104	13
auto[TlIntgErrData]	153	1			T102	8		T103	3		T104	9
auto[TlIntgErrBoth]	144	1			T102	6		T103	3		T104	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4151016

1

T1

990

T2

150

T3

1400

auto[1]

3251874

1

T1

126

T2

884

T3

910

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3042496	1			T1	938		T2	69		T3	688
auto[TlIntgErrNone]	partial	auto[1]	313138	1			T1	36		T2	3		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	1108312	1			T1	52		T2	81		T3	712
auto[TlIntgErrNone]	full_word	auto[1]	2938474	1			T1	90		T2	881		T3	903
auto[TlIntgErrCmd]	partial	auto[0]	69	1			T102	1		T103	4		T104	7
auto[TlIntgErrCmd]	partial	auto[1]	96	1			T102	4		T104	5		T176	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T176	1		T153	1		T183	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T102	1		T104	1		T163	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T102	3		T103	1		T104	3
auto[TlIntgErrData]	partial	auto[1]	77	1			T102	5		T103	2		T104	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T178	1		T180	2		T183	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T184	1		T180	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T102	5		T103	1		T104	5
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T103	2		T104	3		T176	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T102	1		T177	2		T178	2
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T176	1		T177	3		T163	1