Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	2711225	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	2711225	0	0
T2	115008	1663	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	20832	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	0	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T11	394015	0	0	0
T12	0	832	0	0
T13	0	13331	0	0
T14	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	3144494	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	3144494	0	0
T2	115008	832	0	0
T3	61902	3750	0	0
T4	175397	832	0	0
T5	553435	27852	0	0
T6	1633	0	0	0
T7	113837	3887	0	0
T8	637820	0	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T11	394015	0	0	0
T12	0	832	0	0
T13	0	13271	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	188976	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	188976	0	0
T1	5321	42	0	0
T2	115008	0	0	0
T3	61902	0	0	0
T4	175397	0	0	0
T5	553435	2491	0	0
T6	1633	0	0	0
T7	113837	0	0	0
T8	637820	770	0	0
T9	9647	0	0	0
T10	8760	0	0	0
T13	0	354	0	0
T15	0	1166	0	0
T24	0	413	0	0
T26	0	764	0	0
T27	0	4	0	0
T32	0	100	0	0
T35	0	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	455220	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	455220	0	0
T1	5321	42	0	0
T2	115008	0	0	0
T3	61902	0	0	0
T4	175397	0	0	0
T5	553435	7612	0	0
T6	1633	0	0	0
T7	113837	0	0	0
T8	637820	3429	0	0
T9	9647	0	0	0
T10	8760	0	0	0
T13	0	1553	0	0
T15	0	3373	0	0
T24	0	1842	0	0
T26	0	764	0	0
T27	0	4	0	0
T32	0	100	0	0
T35	0	1658	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	5887858	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	5887858	0	0
T1	5321	1074	0	0
T2	115008	202	0	0
T3	61902	1478	0	0
T4	175397	68	0	0
T5	553435	56897	0	0
T6	1633	59	0	0
T7	113837	237	0	0
T8	637820	10240	0	0
T9	9647	188	0	0
T10	8760	412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423292821	12959707	0	0
DepthKnown_A	423292821	423154361	0	0
RvalidKnown_A	423292821	423154361	0	0
WreadyKnown_A	423292821	423154361	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	12959707	0	0
T1	5321	1074	0	0
T2	115008	202	0	0
T3	61902	6464	0	0
T4	175397	68	0	0
T5	553435	189872	0	0
T6	1633	240	0	0
T7	113837	964	0	0
T8	637820	43572	0	0
T9	9647	188	0	0
T10	8760	411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423292821	423154361	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0