Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Unreachable
1	1	Covered	T1,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T35

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T35
1	0	Covered	T5,T13,T35

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T5,T13,T35

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	705990995	562032314	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	705990995	3538853	0	0
GntImpliesValid_A	705990995	3538853	0	0
GrantKnown_A	705990995	562032314	0	0
IdxKnown_A	705990995	562032314	0	0
IndexIsCorrect_A	705990995	3538853	0	0
LockArbDecision_A	705990995	0	0	0
NoReadyValidNoGrant_A	705990995	0	0	0
ReadyAndValidImplyGrant_A	705990995	3538853	0	0
ReqAndReadyImplyGrant_A	705990995	3538853	0	0
ReqImpliesValid_A	705990995	3538853	0	0
ReqStaysHighUntilGranted0_M	705990995	0	0	0
RoundRobin_A	705990995	3	0	974
ValidKnown_A	705990995	562032314	0	0
gen_data_port_assertion.DataFlow_A	705990995	3538853	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	562032314	0	0
T1	9569	9510	0	0
T2	224450	169229	0	0
T3	94710	78014	0	0
T4	520097	347667	0	0
T5	2310917	1419410	0	0
T6	1633	1558	0	0
T7	317433	215546	0	0
T8	820634	724546	0	0
T9	10623	9664	0	0
T10	42964	25765	0	0
T11	190704	90416	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	562032314	0	0
T1	9569	9510	0	0
T2	224450	169229	0	0
T3	94710	78014	0	0
T4	520097	347667	0	0
T5	2310917	1419410	0	0
T6	1633	1558	0	0
T7	317433	215546	0	0
T8	820634	724546	0	0
T9	10623	9664	0	0
T10	42964	25765	0	0
T11	190704	90416	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	562032314	0	0
T1	9569	9510	0	0
T2	224450	169229	0	0
T3	94710	78014	0	0
T4	520097	347667	0	0
T5	2310917	1419410	0	0
T6	1633	1558	0	0
T7	317433	215546	0	0
T8	820634	724546	0	0
T9	10623	9664	0	0
T10	42964	25765	0	0
T11	190704	90416	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3	0	974
T30	315701	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	837	0	0	1
T56	14167	0	0	1
T57	420517	0	0	1
T58	961	0	0	1
T59	124140	0	0	1
T60	1306	0	0	1
T61	489485	0	0	1
T62	39004	0	0	1
T63	444412	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	562032314	0	0
T1	9569	9510	0	0
T2	224450	169229	0	0
T3	94710	78014	0	0
T4	520097	347667	0	0
T5	2310917	1419410	0	0
T6	1633	1558	0	0
T7	317433	215546	0	0
T8	820634	724546	0	0
T9	10623	9664	0	0
T10	42964	25765	0	0
T11	190704	90416	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705990995	3538853	0	0
T1	9569	345	0	0
T2	169729	832	0	0
T3	78306	832	0	0
T4	347747	832	0	0
T5	2310917	35608	0	0
T6	1633	0	0	0
T7	317433	832	0	0
T8	820634	5704	0	0
T9	10623	832	0	0
T10	42964	832	0	0
T11	190704	0	0	0
T12	45966	832	0	0
T13	806502	10041	0	0
T15	0	7427	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T24	0	2270	0	0
T26	0	4310	0	0
T27	0	59	0	0
T35	0	4727	0	0
T40	0	1831	0	0
T41	0	16	0	0
T45	0	3491	0	0
T51	0	44	0	0
T52	0	2402	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Unreachable
1	1	Covered	T1,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142587005	26267077	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	142587005	585258	0	0
GntImpliesValid_A	142587005	585258	0	0
GrantKnown_A	142587005	26267077	0	0
IdxKnown_A	142587005	26267077	0	0
IndexIsCorrect_A	142587005	585258	0	0
LockArbDecision_A	142587005	0	0	0
NoReadyValidNoGrant_A	142587005	0	0	0
ReadyAndValidImplyGrant_A	142587005	585258	0	0
ReqAndReadyImplyGrant_A	142587005	585258	0	0
ReqImpliesValid_A	142587005	585258	0	0
ReqStaysHighUntilGranted0_M	142587005	0	0	0
RoundRobin_A	142587005	0	0	0
ValidKnown_A	142587005	26267077	0	0
gen_data_port_assertion.DataFlow_A	142587005	585258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	26267077	0	0
T1	4248	4248	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	184464	0	0
T7	101798	0	0	0
T8	91407	86792	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	90416	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	26267077	0	0
T1	4248	4248	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	184464	0	0
T7	101798	0	0	0
T8	91407	86792	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	90416	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	26267077	0	0
T1	4248	4248	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	184464	0	0
T7	101798	0	0	0
T8	91407	86792	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	90416	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	26267077	0	0
T1	4248	4248	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	184464	0	0
T7	101798	0	0	0
T8	91407	86792	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	90416	0	0
T15	0	122320	0	0
T22	0	1008	0	0
T23	0	66888	0	0
T24	0	49832	0	0
T26	0	91584	0	0
T27	0	2064	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	585258	0	0
T1	4248	235	0	0
T2	54721	0	0	0
T3	16404	0	0	0
T4	172350	0	0	0
T5	878741	6803	0	0
T7	101798	0	0	0
T8	91407	4013	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T15	0	5148	0	0
T24	0	2270	0	0
T26	0	4309	0	0
T27	0	59	0	0
T40	0	412	0	0
T51	0	44	0	0
T52	0	2402	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T35

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T35
1	0	Covered	T5,T13,T35

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T5,T13,T35

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T13,T35
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T35
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142587005	115035855	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	142587005	820435	0	0
GntImpliesValid_A	142587005	820435	0	0
GrantKnown_A	142587005	115035855	0	0
IdxKnown_A	142587005	115035855	0	0
IndexIsCorrect_A	142587005	820435	0	0
LockArbDecision_A	142587005	0	0	0
NoReadyValidNoGrant_A	142587005	0	0	0
ReadyAndValidImplyGrant_A	142587005	820435	0	0
ReqAndReadyImplyGrant_A	142587005	820435	0	0
ReqImpliesValid_A	142587005	820435	0	0
ReqStaysHighUntilGranted0_M	142587005	0	0	0
RoundRobin_A	142587005	0	0	0
ValidKnown_A	142587005	115035855	0	0
gen_data_port_assertion.DataFlow_A	142587005	820435	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	115035855	0	0
T2	54721	54320	0	0
T3	16404	16208	0	0
T4	172350	172350	0	0
T5	878741	681535	0	0
T7	101798	101798	0	0
T8	91407	0	0	0
T9	488	80	0	0
T10	17102	17102	0	0
T11	95352	0	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	115035855	0	0
T2	54721	54320	0	0
T3	16404	16208	0	0
T4	172350	172350	0	0
T5	878741	681535	0	0
T7	101798	101798	0	0
T8	91407	0	0	0
T9	488	80	0	0
T10	17102	17102	0	0
T11	95352	0	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	115035855	0	0
T2	54721	54320	0	0
T3	16404	16208	0	0
T4	172350	172350	0	0
T5	878741	681535	0	0
T7	101798	101798	0	0
T8	91407	0	0	0
T9	488	80	0	0
T10	17102	17102	0	0
T11	95352	0	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	115035855	0	0
T2	54721	54320	0	0
T3	16404	16208	0	0
T4	172350	172350	0	0
T5	878741	681535	0	0
T7	101798	101798	0	0
T8	91407	0	0	0
T9	488	80	0	0
T10	17102	17102	0	0
T11	95352	0	0	0
T12	45966	45632	0	0
T13	0	803627	0	0
T14	0	27828	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142587005	820435	0	0
T5	878741	10948	0	0
T7	101798	0	0	0
T8	91407	0	0	0
T9	488	0	0	0
T10	17102	0	0	0
T11	95352	0	0	0
T12	45966	0	0	0
T13	806502	10041	0	0
T15	0	2279	0	0
T22	1398	0	0	0
T23	71172	0	0	0
T26	0	1	0	0
T35	0	4727	0	0
T40	0	1419	0	0
T41	0	16	0	0
T42	0	3	0	0
T45	0	3491	0	0
T48	0	3280	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420816985	420729382	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	420816985	2133160	0	0
GntImpliesValid_A	420816985	2133160	0	0
GrantKnown_A	420816985	420729382	0	0
IdxKnown_A	420816985	420729382	0	0
IndexIsCorrect_A	420816985	2133160	0	0
LockArbDecision_A	420816985	0	0	0
NoReadyValidNoGrant_A	420816985	0	0	0
ReadyAndValidImplyGrant_A	420816985	2133160	0	0
ReqAndReadyImplyGrant_A	420816985	2133160	0	0
ReqImpliesValid_A	420816985	2133160	0	0
ReqStaysHighUntilGranted0_M	420816985	0	0	0
RoundRobin_A	420816985	3	0	974
ValidKnown_A	420816985	420729382	0	0
gen_data_port_assertion.DataFlow_A	420816985	2133160	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	420729382	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	420729382	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	420729382	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	3	0	974
T30	315701	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	837	0	0	1
T56	14167	0	0	1
T57	420517	0	0	1
T58	961	0	0	1
T59	124140	0	0	1
T60	1306	0	0	1
T61	489485	0	0	1
T62	39004	0	0	1
T63	444412	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	420729382	0	0
T1	5321	5262	0	0
T2	115008	114909	0	0
T3	61902	61806	0	0
T4	175397	175317	0	0
T5	553435	553411	0	0
T6	1633	1558	0	0
T7	113837	113748	0	0
T8	637820	637754	0	0
T9	9647	9584	0	0
T10	8760	8663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420816985	2133160	0	0
T1	5321	110	0	0
T2	115008	832	0	0
T3	61902	832	0	0
T4	175397	832	0	0
T5	553435	17857	0	0
T6	1633	0	0	0
T7	113837	832	0	0
T8	637820	1691	0	0
T9	9647	832	0	0
T10	8760	832	0	0
T12	0	832	0	0