Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
3394 | 
0 | 
0 | 
| T97 | 
3574 | 
61 | 
0 | 
0 | 
| T98 | 
12078 | 
228 | 
0 | 
0 | 
| T99 | 
6763 | 
119 | 
0 | 
0 | 
| T100 | 
17664 | 
281 | 
0 | 
0 | 
| T101 | 
20195 | 
259 | 
0 | 
0 | 
| T102 | 
70001 | 
3 | 
0 | 
0 | 
| T103 | 
25905 | 
3 | 
0 | 
0 | 
| T110 | 
9416 | 
71 | 
0 | 
0 | 
| T118 | 
3262 | 
5 | 
0 | 
0 | 
| T119 | 
3408 | 
7 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2269 | 
0 | 
0 | 
| T102 | 
70001 | 
101 | 
0 | 
0 | 
| T104 | 
91505 | 
53 | 
0 | 
0 | 
| T142 | 
19707 | 
85 | 
0 | 
0 | 
| T149 | 
18648 | 
16 | 
0 | 
0 | 
| T150 | 
15133 | 
19 | 
0 | 
0 | 
| T151 | 
9085 | 
12 | 
0 | 
0 | 
| T152 | 
7279 | 
38 | 
0 | 
0 | 
| T153 | 
34364 | 
38 | 
0 | 
0 | 
| T154 | 
6886 | 
7 | 
0 | 
0 | 
| T155 | 
8263 | 
5 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2200 | 
0 | 
0 | 
| T102 | 
70001 | 
73 | 
0 | 
0 | 
| T104 | 
91505 | 
77 | 
0 | 
0 | 
| T142 | 
19707 | 
57 | 
0 | 
0 | 
| T149 | 
18648 | 
12 | 
0 | 
0 | 
| T150 | 
15133 | 
15 | 
0 | 
0 | 
| T151 | 
9085 | 
7 | 
0 | 
0 | 
| T152 | 
7279 | 
17 | 
0 | 
0 | 
| T153 | 
34364 | 
44 | 
0 | 
0 | 
| T154 | 
6886 | 
8 | 
0 | 
0 | 
| T156 | 
3918 | 
4 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2758 | 
0 | 
0 | 
| T102 | 
70001 | 
150 | 
0 | 
0 | 
| T104 | 
91505 | 
121 | 
0 | 
0 | 
| T142 | 
19707 | 
27 | 
0 | 
0 | 
| T149 | 
18648 | 
74 | 
0 | 
0 | 
| T150 | 
15133 | 
36 | 
0 | 
0 | 
| T151 | 
9085 | 
5 | 
0 | 
0 | 
| T152 | 
7279 | 
25 | 
0 | 
0 | 
| T153 | 
34364 | 
100 | 
0 | 
0 | 
| T154 | 
6886 | 
15 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
9573 | 
0 | 
0 | 
| T102 | 
70001 | 
1559 | 
0 | 
0 | 
| T104 | 
91505 | 
703 | 
0 | 
0 | 
| T142 | 
19707 | 
23 | 
0 | 
0 | 
| T149 | 
18648 | 
46 | 
0 | 
0 | 
| T150 | 
15133 | 
224 | 
0 | 
0 | 
| T151 | 
9085 | 
61 | 
0 | 
0 | 
| T153 | 
34364 | 
748 | 
0 | 
0 | 
| T154 | 
6886 | 
84 | 
0 | 
0 | 
| T155 | 
8263 | 
70 | 
0 | 
0 | 
| T156 | 
3918 | 
157 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
10321 | 
0 | 
0 | 
| T102 | 
70001 | 
1151 | 
0 | 
0 | 
| T104 | 
91505 | 
1271 | 
0 | 
0 | 
| T142 | 
19707 | 
66 | 
0 | 
0 | 
| T149 | 
18648 | 
25 | 
0 | 
0 | 
| T150 | 
15133 | 
245 | 
0 | 
0 | 
| T151 | 
9085 | 
10 | 
0 | 
0 | 
| T152 | 
7279 | 
37 | 
0 | 
0 | 
| T153 | 
34364 | 
514 | 
0 | 
0 | 
| T154 | 
6886 | 
164 | 
0 | 
0 | 
| T156 | 
3918 | 
147 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
9391 | 
0 | 
0 | 
| T102 | 
70001 | 
1671 | 
0 | 
0 | 
| T104 | 
91505 | 
914 | 
0 | 
0 | 
| T142 | 
19707 | 
86 | 
0 | 
0 | 
| T149 | 
18648 | 
46 | 
0 | 
0 | 
| T150 | 
15133 | 
254 | 
0 | 
0 | 
| T151 | 
9085 | 
6 | 
0 | 
0 | 
| T152 | 
7279 | 
10 | 
0 | 
0 | 
| T153 | 
34364 | 
872 | 
0 | 
0 | 
| T154 | 
6886 | 
60 | 
0 | 
0 | 
| T156 | 
3918 | 
141 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
9249 | 
0 | 
0 | 
| T102 | 
70001 | 
1406 | 
0 | 
0 | 
| T104 | 
91505 | 
1096 | 
0 | 
0 | 
| T142 | 
19707 | 
47 | 
0 | 
0 | 
| T149 | 
18648 | 
24 | 
0 | 
0 | 
| T150 | 
15133 | 
270 | 
0 | 
0 | 
| T151 | 
9085 | 
20 | 
0 | 
0 | 
| T152 | 
7279 | 
13 | 
0 | 
0 | 
| T153 | 
34364 | 
494 | 
0 | 
0 | 
| T154 | 
6886 | 
181 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
9841 | 
0 | 
0 | 
| T102 | 
70001 | 
1650 | 
0 | 
0 | 
| T104 | 
91505 | 
969 | 
0 | 
0 | 
| T106 | 
14892 | 
4 | 
0 | 
0 | 
| T142 | 
19707 | 
41 | 
0 | 
0 | 
| T149 | 
18648 | 
36 | 
0 | 
0 | 
| T150 | 
15133 | 
176 | 
0 | 
0 | 
| T151 | 
9085 | 
85 | 
0 | 
0 | 
| T152 | 
7279 | 
24 | 
0 | 
0 | 
| T153 | 
34364 | 
505 | 
0 | 
0 | 
| T154 | 
6886 | 
15 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
8638 | 
0 | 
0 | 
| T102 | 
70001 | 
1103 | 
0 | 
0 | 
| T104 | 
91505 | 
1058 | 
0 | 
0 | 
| T142 | 
19707 | 
76 | 
0 | 
0 | 
| T149 | 
18648 | 
48 | 
0 | 
0 | 
| T150 | 
15133 | 
32 | 
0 | 
0 | 
| T151 | 
9085 | 
86 | 
0 | 
0 | 
| T152 | 
7279 | 
51 | 
0 | 
0 | 
| T153 | 
34364 | 
592 | 
0 | 
0 | 
| T154 | 
6886 | 
88 | 
0 | 
0 | 
| T156 | 
3918 | 
107 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
7797 | 
0 | 
0 | 
| T102 | 
70001 | 
686 | 
0 | 
0 | 
| T104 | 
91505 | 
1151 | 
0 | 
0 | 
| T142 | 
19707 | 
39 | 
0 | 
0 | 
| T149 | 
18648 | 
48 | 
0 | 
0 | 
| T150 | 
15133 | 
168 | 
0 | 
0 | 
| T151 | 
9085 | 
69 | 
0 | 
0 | 
| T153 | 
34364 | 
894 | 
0 | 
0 | 
| T154 | 
6886 | 
51 | 
0 | 
0 | 
| T155 | 
8263 | 
11 | 
0 | 
0 | 
| T156 | 
3918 | 
9 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
9223 | 
0 | 
0 | 
| T102 | 
70001 | 
1655 | 
0 | 
0 | 
| T104 | 
91505 | 
1062 | 
0 | 
0 | 
| T142 | 
19707 | 
79 | 
0 | 
0 | 
| T149 | 
18648 | 
36 | 
0 | 
0 | 
| T150 | 
15133 | 
264 | 
0 | 
0 | 
| T151 | 
9085 | 
10 | 
0 | 
0 | 
| T153 | 
34364 | 
412 | 
0 | 
0 | 
| T154 | 
6886 | 
117 | 
0 | 
0 | 
| T155 | 
8263 | 
61 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5398 | 
0 | 
0 | 
| T102 | 
70001 | 
576 | 
0 | 
0 | 
| T104 | 
91505 | 
575 | 
0 | 
0 | 
| T142 | 
19707 | 
86 | 
0 | 
0 | 
| T149 | 
18648 | 
25 | 
0 | 
0 | 
| T150 | 
15133 | 
67 | 
0 | 
0 | 
| T151 | 
9085 | 
38 | 
0 | 
0 | 
| T152 | 
7279 | 
4 | 
0 | 
0 | 
| T153 | 
34364 | 
281 | 
0 | 
0 | 
| T154 | 
6886 | 
48 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4687 | 
0 | 
0 | 
| T102 | 
70001 | 
710 | 
0 | 
0 | 
| T104 | 
91505 | 
467 | 
0 | 
0 | 
| T142 | 
19707 | 
48 | 
0 | 
0 | 
| T149 | 
18648 | 
22 | 
0 | 
0 | 
| T150 | 
15133 | 
170 | 
0 | 
0 | 
| T151 | 
9085 | 
37 | 
0 | 
0 | 
| T153 | 
34364 | 
150 | 
0 | 
0 | 
| T154 | 
6886 | 
24 | 
0 | 
0 | 
| T155 | 
8263 | 
34 | 
0 | 
0 | 
| T156 | 
3918 | 
6 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5099 | 
0 | 
0 | 
| T102 | 
70001 | 
614 | 
0 | 
0 | 
| T104 | 
91505 | 
517 | 
0 | 
0 | 
| T142 | 
19707 | 
31 | 
0 | 
0 | 
| T149 | 
18648 | 
35 | 
0 | 
0 | 
| T150 | 
15133 | 
153 | 
0 | 
0 | 
| T151 | 
9085 | 
9 | 
0 | 
0 | 
| T152 | 
7279 | 
65 | 
0 | 
0 | 
| T153 | 
34364 | 
199 | 
0 | 
0 | 
| T154 | 
6886 | 
17 | 
0 | 
0 | 
| T156 | 
3918 | 
7 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5013 | 
0 | 
0 | 
| T102 | 
70001 | 
500 | 
0 | 
0 | 
| T104 | 
91505 | 
319 | 
0 | 
0 | 
| T142 | 
19707 | 
28 | 
0 | 
0 | 
| T149 | 
18648 | 
41 | 
0 | 
0 | 
| T150 | 
15133 | 
22 | 
0 | 
0 | 
| T151 | 
9085 | 
55 | 
0 | 
0 | 
| T152 | 
7279 | 
5 | 
0 | 
0 | 
| T153 | 
34364 | 
286 | 
0 | 
0 | 
| T154 | 
6886 | 
40 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5384 | 
0 | 
0 | 
| T102 | 
70001 | 
802 | 
0 | 
0 | 
| T104 | 
91505 | 
459 | 
0 | 
0 | 
| T106 | 
14892 | 
7 | 
0 | 
0 | 
| T142 | 
19707 | 
36 | 
0 | 
0 | 
| T149 | 
18648 | 
41 | 
0 | 
0 | 
| T150 | 
15133 | 
120 | 
0 | 
0 | 
| T151 | 
9085 | 
42 | 
0 | 
0 | 
| T152 | 
7279 | 
20 | 
0 | 
0 | 
| T153 | 
34364 | 
320 | 
0 | 
0 | 
| T156 | 
3918 | 
56 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5381 | 
0 | 
0 | 
| T102 | 
70001 | 
719 | 
0 | 
0 | 
| T104 | 
91505 | 
466 | 
0 | 
0 | 
| T106 | 
14892 | 
3 | 
0 | 
0 | 
| T142 | 
19707 | 
104 | 
0 | 
0 | 
| T149 | 
18648 | 
73 | 
0 | 
0 | 
| T150 | 
15133 | 
95 | 
0 | 
0 | 
| T151 | 
9085 | 
14 | 
0 | 
0 | 
| T152 | 
7279 | 
34 | 
0 | 
0 | 
| T153 | 
34364 | 
306 | 
0 | 
0 | 
| T156 | 
3918 | 
68 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4923 | 
0 | 
0 | 
| T102 | 
70001 | 
536 | 
0 | 
0 | 
| T104 | 
91505 | 
539 | 
0 | 
0 | 
| T106 | 
14892 | 
9 | 
0 | 
0 | 
| T142 | 
19707 | 
78 | 
0 | 
0 | 
| T149 | 
18648 | 
34 | 
0 | 
0 | 
| T150 | 
15133 | 
74 | 
0 | 
0 | 
| T151 | 
9085 | 
1 | 
0 | 
0 | 
| T152 | 
7279 | 
25 | 
0 | 
0 | 
| T153 | 
34364 | 
362 | 
0 | 
0 | 
| T156 | 
3918 | 
3 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4794 | 
0 | 
0 | 
| T102 | 
70001 | 
638 | 
0 | 
0 | 
| T104 | 
91505 | 
475 | 
0 | 
0 | 
| T142 | 
19707 | 
28 | 
0 | 
0 | 
| T149 | 
18648 | 
53 | 
0 | 
0 | 
| T150 | 
15133 | 
179 | 
0 | 
0 | 
| T151 | 
9085 | 
4 | 
0 | 
0 | 
| T152 | 
7279 | 
26 | 
0 | 
0 | 
| T153 | 
34364 | 
293 | 
0 | 
0 | 
| T154 | 
6886 | 
27 | 
0 | 
0 | 
| T156 | 
3918 | 
5 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4828 | 
0 | 
0 | 
| T102 | 
70001 | 
476 | 
0 | 
0 | 
| T104 | 
91505 | 
273 | 
0 | 
0 | 
| T142 | 
19707 | 
80 | 
0 | 
0 | 
| T149 | 
18648 | 
27 | 
0 | 
0 | 
| T150 | 
15133 | 
81 | 
0 | 
0 | 
| T151 | 
9085 | 
34 | 
0 | 
0 | 
| T152 | 
7279 | 
24 | 
0 | 
0 | 
| T153 | 
34364 | 
306 | 
0 | 
0 | 
| T154 | 
6886 | 
35 | 
0 | 
0 | 
| T156 | 
3918 | 
65 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5778 | 
0 | 
0 | 
| T99 | 
6763 | 
1 | 
0 | 
0 | 
| T102 | 
70001 | 
699 | 
0 | 
0 | 
| T104 | 
91505 | 
512 | 
0 | 
0 | 
| T142 | 
19707 | 
45 | 
0 | 
0 | 
| T149 | 
18648 | 
14 | 
0 | 
0 | 
| T150 | 
15133 | 
133 | 
0 | 
0 | 
| T151 | 
9085 | 
21 | 
0 | 
0 | 
| T152 | 
7279 | 
7 | 
0 | 
0 | 
| T153 | 
34364 | 
415 | 
0 | 
0 | 
| T156 | 
3918 | 
6 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4839 | 
0 | 
0 | 
| T101 | 
20195 | 
7 | 
0 | 
0 | 
| T102 | 
70001 | 
837 | 
0 | 
0 | 
| T104 | 
91505 | 
387 | 
0 | 
0 | 
| T142 | 
19707 | 
53 | 
0 | 
0 | 
| T149 | 
18648 | 
36 | 
0 | 
0 | 
| T150 | 
15133 | 
76 | 
0 | 
0 | 
| T151 | 
9085 | 
53 | 
0 | 
0 | 
| T152 | 
7279 | 
18 | 
0 | 
0 | 
| T153 | 
34364 | 
287 | 
0 | 
0 | 
| T156 | 
3918 | 
56 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4953 | 
0 | 
0 | 
| T102 | 
70001 | 
589 | 
0 | 
0 | 
| T104 | 
91505 | 
390 | 
0 | 
0 | 
| T142 | 
19707 | 
86 | 
0 | 
0 | 
| T149 | 
18648 | 
31 | 
0 | 
0 | 
| T150 | 
15133 | 
150 | 
0 | 
0 | 
| T151 | 
9085 | 
38 | 
0 | 
0 | 
| T152 | 
7279 | 
7 | 
0 | 
0 | 
| T153 | 
34364 | 
287 | 
0 | 
0 | 
| T154 | 
6886 | 
22 | 
0 | 
0 | 
| T156 | 
3918 | 
60 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4724 | 
0 | 
0 | 
| T102 | 
70001 | 
681 | 
0 | 
0 | 
| T104 | 
91505 | 
431 | 
0 | 
0 | 
| T142 | 
19707 | 
68 | 
0 | 
0 | 
| T149 | 
18648 | 
40 | 
0 | 
0 | 
| T150 | 
15133 | 
99 | 
0 | 
0 | 
| T151 | 
9085 | 
36 | 
0 | 
0 | 
| T152 | 
7279 | 
7 | 
0 | 
0 | 
| T153 | 
34364 | 
221 | 
0 | 
0 | 
| T154 | 
6886 | 
66 | 
0 | 
0 | 
| T156 | 
3918 | 
61 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5218 | 
0 | 
0 | 
| T102 | 
70001 | 
605 | 
0 | 
0 | 
| T104 | 
91505 | 
396 | 
0 | 
0 | 
| T142 | 
19707 | 
93 | 
0 | 
0 | 
| T149 | 
18648 | 
26 | 
0 | 
0 | 
| T150 | 
15133 | 
29 | 
0 | 
0 | 
| T151 | 
9085 | 
35 | 
0 | 
0 | 
| T152 | 
7279 | 
17 | 
0 | 
0 | 
| T153 | 
34364 | 
361 | 
0 | 
0 | 
| T154 | 
6886 | 
21 | 
0 | 
0 | 
| T156 | 
3918 | 
53 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5361 | 
0 | 
0 | 
| T102 | 
70001 | 
522 | 
0 | 
0 | 
| T104 | 
91505 | 
467 | 
0 | 
0 | 
| T142 | 
19707 | 
55 | 
0 | 
0 | 
| T149 | 
18648 | 
33 | 
0 | 
0 | 
| T150 | 
15133 | 
119 | 
0 | 
0 | 
| T152 | 
7279 | 
34 | 
0 | 
0 | 
| T153 | 
34364 | 
279 | 
0 | 
0 | 
| T154 | 
6886 | 
58 | 
0 | 
0 | 
| T155 | 
8263 | 
16 | 
0 | 
0 | 
| T156 | 
3918 | 
59 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4676 | 
0 | 
0 | 
| T102 | 
70001 | 
377 | 
0 | 
0 | 
| T104 | 
91505 | 
454 | 
0 | 
0 | 
| T106 | 
14892 | 
3 | 
0 | 
0 | 
| T142 | 
19707 | 
40 | 
0 | 
0 | 
| T149 | 
18648 | 
45 | 
0 | 
0 | 
| T150 | 
15133 | 
54 | 
0 | 
0 | 
| T151 | 
9085 | 
36 | 
0 | 
0 | 
| T152 | 
7279 | 
1 | 
0 | 
0 | 
| T153 | 
34364 | 
373 | 
0 | 
0 | 
| T156 | 
3918 | 
68 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4964 | 
0 | 
0 | 
| T102 | 
70001 | 
505 | 
0 | 
0 | 
| T104 | 
91505 | 
585 | 
0 | 
0 | 
| T142 | 
19707 | 
43 | 
0 | 
0 | 
| T149 | 
18648 | 
58 | 
0 | 
0 | 
| T150 | 
15133 | 
83 | 
0 | 
0 | 
| T151 | 
9085 | 
1 | 
0 | 
0 | 
| T152 | 
7279 | 
30 | 
0 | 
0 | 
| T153 | 
34364 | 
436 | 
0 | 
0 | 
| T154 | 
6886 | 
25 | 
0 | 
0 | 
| T156 | 
3918 | 
54 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5096 | 
0 | 
0 | 
| T102 | 
70001 | 
557 | 
0 | 
0 | 
| T104 | 
91505 | 
487 | 
0 | 
0 | 
| T142 | 
19707 | 
47 | 
0 | 
0 | 
| T149 | 
18648 | 
54 | 
0 | 
0 | 
| T150 | 
15133 | 
24 | 
0 | 
0 | 
| T151 | 
9085 | 
20 | 
0 | 
0 | 
| T152 | 
7279 | 
25 | 
0 | 
0 | 
| T153 | 
34364 | 
238 | 
0 | 
0 | 
| T154 | 
6886 | 
25 | 
0 | 
0 | 
| T156 | 
3918 | 
49 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
5144 | 
0 | 
0 | 
| T102 | 
70001 | 
494 | 
0 | 
0 | 
| T104 | 
91505 | 
415 | 
0 | 
0 | 
| T142 | 
19707 | 
83 | 
0 | 
0 | 
| T149 | 
18648 | 
44 | 
0 | 
0 | 
| T150 | 
15133 | 
74 | 
0 | 
0 | 
| T151 | 
9085 | 
52 | 
0 | 
0 | 
| T152 | 
7279 | 
32 | 
0 | 
0 | 
| T153 | 
34364 | 
435 | 
0 | 
0 | 
| T154 | 
6886 | 
15 | 
0 | 
0 | 
| T156 | 
3918 | 
1 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4849 | 
0 | 
0 | 
| T102 | 
70001 | 
431 | 
0 | 
0 | 
| T104 | 
91505 | 
436 | 
0 | 
0 | 
| T142 | 
19707 | 
54 | 
0 | 
0 | 
| T149 | 
18648 | 
37 | 
0 | 
0 | 
| T150 | 
15133 | 
149 | 
0 | 
0 | 
| T151 | 
9085 | 
34 | 
0 | 
0 | 
| T152 | 
7279 | 
21 | 
0 | 
0 | 
| T153 | 
34364 | 
239 | 
0 | 
0 | 
| T154 | 
6886 | 
1 | 
0 | 
0 | 
| T156 | 
3918 | 
7 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4924 | 
0 | 
0 | 
| T102 | 
70001 | 
611 | 
0 | 
0 | 
| T104 | 
91505 | 
499 | 
0 | 
0 | 
| T142 | 
19707 | 
88 | 
0 | 
0 | 
| T149 | 
18648 | 
14 | 
0 | 
0 | 
| T150 | 
15133 | 
73 | 
0 | 
0 | 
| T151 | 
9085 | 
6 | 
0 | 
0 | 
| T153 | 
34364 | 
223 | 
0 | 
0 | 
| T154 | 
6886 | 
8 | 
0 | 
0 | 
| T155 | 
8263 | 
19 | 
0 | 
0 | 
| T156 | 
3918 | 
44 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4467 | 
0 | 
0 | 
| T102 | 
70001 | 
479 | 
0 | 
0 | 
| T104 | 
91505 | 
271 | 
0 | 
0 | 
| T142 | 
19707 | 
48 | 
0 | 
0 | 
| T149 | 
18648 | 
14 | 
0 | 
0 | 
| T150 | 
15133 | 
14 | 
0 | 
0 | 
| T151 | 
9085 | 
42 | 
0 | 
0 | 
| T152 | 
7279 | 
30 | 
0 | 
0 | 
| T153 | 
34364 | 
187 | 
0 | 
0 | 
| T154 | 
6886 | 
13 | 
0 | 
0 | 
| T156 | 
3918 | 
2 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4612 | 
0 | 
0 | 
| T102 | 
70001 | 
319 | 
0 | 
0 | 
| T104 | 
91505 | 
395 | 
0 | 
0 | 
| T142 | 
19707 | 
74 | 
0 | 
0 | 
| T149 | 
18648 | 
24 | 
0 | 
0 | 
| T150 | 
15133 | 
82 | 
0 | 
0 | 
| T151 | 
9085 | 
61 | 
0 | 
0 | 
| T152 | 
7279 | 
4 | 
0 | 
0 | 
| T153 | 
34364 | 
243 | 
0 | 
0 | 
| T155 | 
8263 | 
54 | 
0 | 
0 | 
| T156 | 
3918 | 
1 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4940 | 
0 | 
0 | 
| T102 | 
70001 | 
651 | 
0 | 
0 | 
| T104 | 
91505 | 
317 | 
0 | 
0 | 
| T142 | 
19707 | 
50 | 
0 | 
0 | 
| T149 | 
18648 | 
43 | 
0 | 
0 | 
| T150 | 
15133 | 
59 | 
0 | 
0 | 
| T151 | 
9085 | 
21 | 
0 | 
0 | 
| T152 | 
7279 | 
14 | 
0 | 
0 | 
| T153 | 
34364 | 
272 | 
0 | 
0 | 
| T154 | 
6886 | 
48 | 
0 | 
0 | 
| T155 | 
8263 | 
43 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2465 | 
0 | 
0 | 
| T102 | 
70001 | 
133 | 
0 | 
0 | 
| T104 | 
91505 | 
78 | 
0 | 
0 | 
| T142 | 
19707 | 
44 | 
0 | 
0 | 
| T149 | 
18648 | 
42 | 
0 | 
0 | 
| T150 | 
15133 | 
48 | 
0 | 
0 | 
| T151 | 
9085 | 
1 | 
0 | 
0 | 
| T152 | 
7279 | 
2 | 
0 | 
0 | 
| T153 | 
34364 | 
59 | 
0 | 
0 | 
| T154 | 
6886 | 
1 | 
0 | 
0 | 
| T156 | 
3918 | 
3 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2655 | 
0 | 
0 | 
| T101 | 
20195 | 
5 | 
0 | 
0 | 
| T102 | 
70001 | 
136 | 
0 | 
0 | 
| T104 | 
91505 | 
102 | 
0 | 
0 | 
| T142 | 
19707 | 
34 | 
0 | 
0 | 
| T149 | 
18648 | 
62 | 
0 | 
0 | 
| T150 | 
15133 | 
25 | 
0 | 
0 | 
| T151 | 
9085 | 
13 | 
0 | 
0 | 
| T152 | 
7279 | 
33 | 
0 | 
0 | 
| T153 | 
34364 | 
53 | 
0 | 
0 | 
| T156 | 
3918 | 
4 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2561 | 
0 | 
0 | 
| T102 | 
70001 | 
105 | 
0 | 
0 | 
| T104 | 
91505 | 
85 | 
0 | 
0 | 
| T142 | 
19707 | 
56 | 
0 | 
0 | 
| T149 | 
18648 | 
10 | 
0 | 
0 | 
| T150 | 
15133 | 
14 | 
0 | 
0 | 
| T151 | 
9085 | 
24 | 
0 | 
0 | 
| T152 | 
7279 | 
54 | 
0 | 
0 | 
| T153 | 
34364 | 
60 | 
0 | 
0 | 
| T155 | 
8263 | 
5 | 
0 | 
0 | 
| T156 | 
3918 | 
1 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2513 | 
0 | 
0 | 
| T102 | 
70001 | 
120 | 
0 | 
0 | 
| T104 | 
91505 | 
77 | 
0 | 
0 | 
| T142 | 
19707 | 
67 | 
0 | 
0 | 
| T149 | 
18648 | 
17 | 
0 | 
0 | 
| T150 | 
15133 | 
35 | 
0 | 
0 | 
| T151 | 
9085 | 
6 | 
0 | 
0 | 
| T152 | 
7279 | 
41 | 
0 | 
0 | 
| T153 | 
34364 | 
55 | 
0 | 
0 | 
| T154 | 
6886 | 
14 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2751 | 
0 | 
0 | 
| T102 | 
70001 | 
159 | 
0 | 
0 | 
| T104 | 
91505 | 
158 | 
0 | 
0 | 
| T142 | 
19707 | 
69 | 
0 | 
0 | 
| T149 | 
18648 | 
46 | 
0 | 
0 | 
| T150 | 
15133 | 
28 | 
0 | 
0 | 
| T151 | 
9085 | 
31 | 
0 | 
0 | 
| T152 | 
7279 | 
16 | 
0 | 
0 | 
| T153 | 
34364 | 
62 | 
0 | 
0 | 
| T154 | 
6886 | 
12 | 
0 | 
0 | 
| T156 | 
3918 | 
22 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
4785 | 
0 | 
0 | 
| T15 | 
502489 | 
3 | 
0 | 
0 | 
| T17 | 
0 | 
2 | 
0 | 
0 | 
| T20 | 
0 | 
22 | 
0 | 
0 | 
| T27 | 
3086 | 
0 | 
0 | 
0 | 
| T32 | 
1298 | 
0 | 
0 | 
0 | 
| T33 | 
2235 | 
0 | 
0 | 
0 | 
| T47 | 
258104 | 
0 | 
0 | 
0 | 
| T51 | 
7426 | 
0 | 
0 | 
0 | 
| T65 | 
1102 | 
0 | 
0 | 
0 | 
| T83 | 
452348 | 
0 | 
0 | 
0 | 
| T84 | 
801303 | 
0 | 
0 | 
0 | 
| T92 | 
563110 | 
0 | 
0 | 
0 | 
| T137 | 
0 | 
19 | 
0 | 
0 | 
| T157 | 
0 | 
24 | 
0 | 
0 | 
| T158 | 
0 | 
14 | 
0 | 
0 | 
| T159 | 
0 | 
32 | 
0 | 
0 | 
| T160 | 
0 | 
46 | 
0 | 
0 | 
| T161 | 
0 | 
70 | 
0 | 
0 | 
| T162 | 
0 | 
28 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2577 | 
0 | 
0 | 
| T102 | 
70001 | 
118 | 
0 | 
0 | 
| T104 | 
91505 | 
87 | 
0 | 
0 | 
| T142 | 
19707 | 
23 | 
0 | 
0 | 
| T149 | 
18648 | 
16 | 
0 | 
0 | 
| T150 | 
15133 | 
24 | 
0 | 
0 | 
| T151 | 
9085 | 
22 | 
0 | 
0 | 
| T152 | 
7279 | 
46 | 
0 | 
0 | 
| T153 | 
34364 | 
43 | 
0 | 
0 | 
| T154 | 
6886 | 
10 | 
0 | 
0 | 
| T156 | 
3918 | 
9 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2393 | 
0 | 
0 | 
| T102 | 
70001 | 
137 | 
0 | 
0 | 
| T104 | 
91505 | 
110 | 
0 | 
0 | 
| T142 | 
19707 | 
34 | 
0 | 
0 | 
| T149 | 
18648 | 
33 | 
0 | 
0 | 
| T150 | 
15133 | 
31 | 
0 | 
0 | 
| T151 | 
9085 | 
7 | 
0 | 
0 | 
| T152 | 
7279 | 
23 | 
0 | 
0 | 
| T153 | 
34364 | 
59 | 
0 | 
0 | 
| T154 | 
6886 | 
7 | 
0 | 
0 | 
| T156 | 
3918 | 
15 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2270 | 
0 | 
0 | 
| T102 | 
70001 | 
82 | 
0 | 
0 | 
| T104 | 
91505 | 
48 | 
0 | 
0 | 
| T142 | 
19707 | 
24 | 
0 | 
0 | 
| T149 | 
18648 | 
52 | 
0 | 
0 | 
| T150 | 
15133 | 
32 | 
0 | 
0 | 
| T151 | 
9085 | 
4 | 
0 | 
0 | 
| T152 | 
7279 | 
27 | 
0 | 
0 | 
| T153 | 
34364 | 
48 | 
0 | 
0 | 
| T154 | 
6886 | 
3 | 
0 | 
0 | 
| T156 | 
3918 | 
5 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2192 | 
0 | 
0 | 
| T102 | 
70001 | 
71 | 
0 | 
0 | 
| T104 | 
91505 | 
57 | 
0 | 
0 | 
| T142 | 
19707 | 
77 | 
0 | 
0 | 
| T149 | 
18648 | 
9 | 
0 | 
0 | 
| T150 | 
15133 | 
29 | 
0 | 
0 | 
| T151 | 
9085 | 
3 | 
0 | 
0 | 
| T152 | 
7279 | 
6 | 
0 | 
0 | 
| T153 | 
34364 | 
35 | 
0 | 
0 | 
| T154 | 
6886 | 
6 | 
0 | 
0 | 
| T156 | 
3918 | 
8 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2254 | 
0 | 
0 | 
| T102 | 
70001 | 
64 | 
0 | 
0 | 
| T104 | 
91505 | 
40 | 
0 | 
0 | 
| T142 | 
19707 | 
62 | 
0 | 
0 | 
| T149 | 
18648 | 
57 | 
0 | 
0 | 
| T150 | 
15133 | 
13 | 
0 | 
0 | 
| T151 | 
9085 | 
7 | 
0 | 
0 | 
| T152 | 
7279 | 
6 | 
0 | 
0 | 
| T153 | 
34364 | 
32 | 
0 | 
0 | 
| T154 | 
6886 | 
1 | 
0 | 
0 | 
| T156 | 
3918 | 
2 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2311 | 
0 | 
0 | 
| T101 | 
20195 | 
2 | 
0 | 
0 | 
| T102 | 
70001 | 
72 | 
0 | 
0 | 
| T104 | 
91505 | 
62 | 
0 | 
0 | 
| T142 | 
19707 | 
99 | 
0 | 
0 | 
| T149 | 
18648 | 
32 | 
0 | 
0 | 
| T150 | 
15133 | 
28 | 
0 | 
0 | 
| T151 | 
9085 | 
17 | 
0 | 
0 | 
| T152 | 
7279 | 
44 | 
0 | 
0 | 
| T153 | 
34364 | 
33 | 
0 | 
0 | 
| T156 | 
3918 | 
9 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
3080 | 
0 | 
0 | 
| T102 | 
70001 | 
175 | 
0 | 
0 | 
| T104 | 
91505 | 
174 | 
0 | 
0 | 
| T142 | 
19707 | 
90 | 
0 | 
0 | 
| T149 | 
18648 | 
51 | 
0 | 
0 | 
| T150 | 
15133 | 
21 | 
0 | 
0 | 
| T151 | 
9085 | 
10 | 
0 | 
0 | 
| T152 | 
7279 | 
54 | 
0 | 
0 | 
| T153 | 
34364 | 
117 | 
0 | 
0 | 
| T154 | 
6886 | 
9 | 
0 | 
0 | 
| T156 | 
3918 | 
16 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2343 | 
0 | 
0 | 
| T102 | 
70001 | 
83 | 
0 | 
0 | 
| T104 | 
91505 | 
59 | 
0 | 
0 | 
| T142 | 
19707 | 
71 | 
0 | 
0 | 
| T149 | 
18648 | 
9 | 
0 | 
0 | 
| T150 | 
15133 | 
21 | 
0 | 
0 | 
| T151 | 
9085 | 
11 | 
0 | 
0 | 
| T152 | 
7279 | 
28 | 
0 | 
0 | 
| T153 | 
34364 | 
45 | 
0 | 
0 | 
| T154 | 
6886 | 
9 | 
0 | 
0 | 
| T156 | 
3918 | 
7 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2948 | 
0 | 
0 | 
| T102 | 
70001 | 
214 | 
0 | 
0 | 
| T104 | 
91505 | 
172 | 
0 | 
0 | 
| T142 | 
19707 | 
77 | 
0 | 
0 | 
| T149 | 
18648 | 
17 | 
0 | 
0 | 
| T150 | 
15133 | 
20 | 
0 | 
0 | 
| T151 | 
9085 | 
21 | 
0 | 
0 | 
| T152 | 
7279 | 
23 | 
0 | 
0 | 
| T153 | 
34364 | 
82 | 
0 | 
0 | 
| T155 | 
8263 | 
28 | 
0 | 
0 | 
| T156 | 
3918 | 
5 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2452 | 
0 | 
0 | 
| T102 | 
70001 | 
129 | 
0 | 
0 | 
| T104 | 
91505 | 
85 | 
0 | 
0 | 
| T142 | 
19707 | 
50 | 
0 | 
0 | 
| T149 | 
18648 | 
6 | 
0 | 
0 | 
| T150 | 
15133 | 
18 | 
0 | 
0 | 
| T151 | 
9085 | 
27 | 
0 | 
0 | 
| T152 | 
7279 | 
4 | 
0 | 
0 | 
| T153 | 
34364 | 
51 | 
0 | 
0 | 
| T154 | 
6886 | 
7 | 
0 | 
0 | 
| T156 | 
3918 | 
9 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2420 | 
0 | 
0 | 
| T99 | 
6763 | 
3 | 
0 | 
0 | 
| T102 | 
70001 | 
83 | 
0 | 
0 | 
| T104 | 
91505 | 
54 | 
0 | 
0 | 
| T142 | 
19707 | 
95 | 
0 | 
0 | 
| T149 | 
18648 | 
21 | 
0 | 
0 | 
| T150 | 
15133 | 
31 | 
0 | 
0 | 
| T151 | 
9085 | 
13 | 
0 | 
0 | 
| T152 | 
7279 | 
43 | 
0 | 
0 | 
| T153 | 
34364 | 
42 | 
0 | 
0 | 
| T155 | 
8263 | 
9 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2254 | 
0 | 
0 | 
| T102 | 
70001 | 
70 | 
0 | 
0 | 
| T104 | 
91505 | 
73 | 
0 | 
0 | 
| T106 | 
14892 | 
8 | 
0 | 
0 | 
| T142 | 
19707 | 
45 | 
0 | 
0 | 
| T149 | 
18648 | 
35 | 
0 | 
0 | 
| T150 | 
15133 | 
23 | 
0 | 
0 | 
| T151 | 
9085 | 
18 | 
0 | 
0 | 
| T152 | 
7279 | 
32 | 
0 | 
0 | 
| T153 | 
34364 | 
55 | 
0 | 
0 | 
| T156 | 
3918 | 
6 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2487 | 
0 | 
0 | 
| T102 | 
70001 | 
96 | 
0 | 
0 | 
| T104 | 
91505 | 
82 | 
0 | 
0 | 
| T142 | 
19707 | 
21 | 
0 | 
0 | 
| T149 | 
18648 | 
22 | 
0 | 
0 | 
| T150 | 
15133 | 
19 | 
0 | 
0 | 
| T152 | 
7279 | 
34 | 
0 | 
0 | 
| T153 | 
34364 | 
54 | 
0 | 
0 | 
| T154 | 
6886 | 
9 | 
0 | 
0 | 
| T155 | 
8263 | 
9 | 
0 | 
0 | 
| T163 | 
60280 | 
32 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2246 | 
0 | 
0 | 
| T102 | 
70001 | 
50 | 
0 | 
0 | 
| T104 | 
91505 | 
34 | 
0 | 
0 | 
| T142 | 
19707 | 
43 | 
0 | 
0 | 
| T149 | 
18648 | 
29 | 
0 | 
0 | 
| T150 | 
15133 | 
24 | 
0 | 
0 | 
| T152 | 
7279 | 
8 | 
0 | 
0 | 
| T153 | 
34364 | 
28 | 
0 | 
0 | 
| T155 | 
8263 | 
2 | 
0 | 
0 | 
| T156 | 
3918 | 
3 | 
0 | 
0 | 
| T163 | 
60280 | 
51 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2379 | 
0 | 
0 | 
| T102 | 
70001 | 
71 | 
0 | 
0 | 
| T104 | 
91505 | 
43 | 
0 | 
0 | 
| T142 | 
19707 | 
94 | 
0 | 
0 | 
| T149 | 
18648 | 
51 | 
0 | 
0 | 
| T150 | 
15133 | 
22 | 
0 | 
0 | 
| T151 | 
9085 | 
8 | 
0 | 
0 | 
| T152 | 
7279 | 
12 | 
0 | 
0 | 
| T153 | 
34364 | 
49 | 
0 | 
0 | 
| T154 | 
6886 | 
3 | 
0 | 
0 | 
| T155 | 
8263 | 
9 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
423292821 | 
2350 | 
0 | 
0 | 
| T102 | 
70001 | 
75 | 
0 | 
0 | 
| T104 | 
91505 | 
54 | 
0 | 
0 | 
| T142 | 
19707 | 
51 | 
0 | 
0 | 
| T149 | 
18648 | 
35 | 
0 | 
0 | 
| T150 | 
15133 | 
30 | 
0 | 
0 | 
| T151 | 
9085 | 
13 | 
0 | 
0 | 
| T152 | 
7279 | 
29 | 
0 | 
0 | 
| T153 | 
34364 | 
53 | 
0 | 
0 | 
| T154 | 
6886 | 
6 | 
0 | 
0 | 
| T156 | 
3918 | 
4 | 
0 | 
0 |