Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3325910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4062487

1

T1

2151

T2

1138

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3964252	1			T1	2461		T2	510		T3	1
values[0x0]	1711338	1			T1	453		T2	422		T3	10
values[0x1]	1712807	1			T1	471		T2	463		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2353622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5034775

1

T1

2433

T2

1194

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28323	1			T4	63		T5	22		T6	1
valid_sources[0x01]	28043	1			T4	70		T5	30		T6	4
valid_sources[0x02]	28241	1			T4	68		T5	35		T6	2
valid_sources[0x03]	27175	1			T4	62		T5	32		T6	1
valid_sources[0x04]	25414	1			T4	85		T5	15		T6	3
valid_sources[0x05]	28520	1			T4	61		T5	26		T6	4
valid_sources[0x06]	28807	1			T4	116		T5	26		T6	6
valid_sources[0x07]	25241	1			T4	49		T5	21		T6	6
valid_sources[0x08]	26965	1			T3	2		T4	83		T5	21
valid_sources[0x09]	28288	1			T4	53		T5	24		T6	3
valid_sources[0x0a]	29290	1			T3	1		T4	61		T5	20
valid_sources[0x0b]	28771	1			T4	50		T5	17		T6	5
valid_sources[0x0c]	28577	1			T1	1		T4	76		T5	36
valid_sources[0x0d]	28415	1			T4	91		T5	25		T6	1
valid_sources[0x0e]	26720	1			T4	54		T5	14		T6	3
valid_sources[0x0f]	29465	1			T1	1		T4	74		T5	13
valid_sources[0x10]	28897	1			T4	90		T5	15		T6	6
valid_sources[0x11]	28921	1			T4	59		T5	9		T6	4
valid_sources[0x12]	26161	1			T4	76		T5	26		T6	4
valid_sources[0x13]	27484	1			T4	78		T5	33		T6	7
valid_sources[0x14]	25965	1			T4	58		T5	10		T6	6
valid_sources[0x15]	29151	1			T4	76		T5	30		T6	2
valid_sources[0x16]	28408	1			T4	60		T5	22		T6	1
valid_sources[0x17]	28148	1			T4	65		T5	31		T6	5
valid_sources[0x18]	26896	1			T4	67		T5	22		T6	3
valid_sources[0x19]	29968	1			T4	55		T5	24		T6	5
valid_sources[0x1a]	28703	1			T4	40		T5	23		T6	6
valid_sources[0x1b]	28948	1			T4	73		T5	25		T6	4
valid_sources[0x1c]	31712	1			T4	56		T5	20		T6	8
valid_sources[0x1d]	27071	1			T2	1		T4	80		T5	22
valid_sources[0x1e]	27785	1			T4	58		T5	23		T6	5
valid_sources[0x1f]	27112	1			T2	1		T4	100		T5	21
valid_sources[0x20]	28948	1			T4	86		T5	11		T6	4
valid_sources[0x21]	28989	1			T4	91		T5	35		T6	2
valid_sources[0x22]	27270	1			T4	76		T5	10		T6	5
valid_sources[0x23]	28938	1			T4	71		T5	13		T6	4
valid_sources[0x24]	31596	1			T4	90		T5	41		T6	3
valid_sources[0x25]	29225	1			T4	47		T5	40		T6	5
valid_sources[0x26]	26477	1			T4	53		T5	27		T6	1
valid_sources[0x27]	27943	1			T4	63		T5	12		T7	25
valid_sources[0x28]	27316	1			T4	50		T5	24		T6	4
valid_sources[0x29]	41902	1			T4	59		T5	36		T6	1
valid_sources[0x2a]	26936	1			T4	74		T5	16		T6	5
valid_sources[0x2b]	28074	1			T4	56		T5	18		T6	4
valid_sources[0x2c]	26906	1			T4	55		T5	23		T6	5
valid_sources[0x2d]	27882	1			T4	59		T5	29		T6	5
valid_sources[0x2e]	34570	1			T4	57		T5	25		T6	1
valid_sources[0x2f]	29094	1			T4	90		T5	22		T6	4
valid_sources[0x30]	31194	1			T4	50		T5	35		T6	3
valid_sources[0x31]	27814	1			T4	69		T5	45		T6	1
valid_sources[0x32]	33687	1			T2	1		T4	85		T5	19
valid_sources[0x33]	29957	1			T4	56		T5	17		T6	5
valid_sources[0x34]	29768	1			T4	74		T5	21		T6	1
valid_sources[0x35]	26440	1			T4	37		T5	35		T6	2
valid_sources[0x36]	30398	1			T4	87		T5	27		T6	2
valid_sources[0x37]	26206	1			T4	58		T5	41		T6	3
valid_sources[0x38]	32750	1			T4	73		T5	42		T6	1
valid_sources[0x39]	29364	1			T4	101		T5	32		T6	5
valid_sources[0x3a]	28984	1			T4	86		T5	30		T6	2
valid_sources[0x3b]	28926	1			T4	64		T5	24		T6	9
valid_sources[0x3c]	29443	1			T4	62		T5	23		T6	1
valid_sources[0x3d]	26528	1			T4	72		T5	33		T6	6
valid_sources[0x3e]	29826	1			T4	68		T5	30		T6	3
valid_sources[0x3f]	27187	1			T4	64		T5	24		T6	4
valid_sources[0x40]	27900	1			T4	106		T5	9		T6	9
valid_sources[0x41]	28575	1			T4	88		T5	18		T6	4
valid_sources[0x42]	27353	1			T4	63		T5	11		T6	3
valid_sources[0x43]	26989	1			T4	70		T5	30		T6	1
valid_sources[0x44]	25902	1			T4	80		T5	37		T6	8
valid_sources[0x45]	29316	1			T3	6		T4	75		T5	16
valid_sources[0x46]	34514	1			T4	79		T5	22		T6	3
valid_sources[0x47]	44186	1			T4	64		T5	15		T7	34
valid_sources[0x48]	28657	1			T4	51		T5	12		T6	3
valid_sources[0x49]	25528	1			T4	54		T5	24		T6	3
valid_sources[0x4a]	31640	1			T4	58		T5	24		T6	1
valid_sources[0x4b]	29969	1			T4	80		T5	32		T6	6
valid_sources[0x4c]	27685	1			T4	35		T5	28		T6	4
valid_sources[0x4d]	28396	1			T4	55		T5	11		T6	5
valid_sources[0x4e]	28150	1			T4	60		T5	13		T6	1
valid_sources[0x4f]	31164	1			T4	85		T5	32		T6	4
valid_sources[0x50]	28240	1			T4	78		T5	13		T6	1
valid_sources[0x51]	28117	1			T4	75		T5	39		T6	1
valid_sources[0x52]	28077	1			T4	61		T5	25		T6	2
valid_sources[0x53]	27774	1			T2	1		T4	61		T5	35
valid_sources[0x54]	26426	1			T3	3		T4	47		T5	30
valid_sources[0x55]	31193	1			T3	5		T4	74		T5	32
valid_sources[0x56]	28026	1			T4	73		T5	22		T6	2
valid_sources[0x57]	27178	1			T1	452		T4	53		T5	36
valid_sources[0x58]	33257	1			T4	52		T5	27		T6	1
valid_sources[0x59]	26778	1			T4	64		T5	11		T6	4
valid_sources[0x5a]	34658	1			T4	54		T5	32		T6	1
valid_sources[0x5b]	25717	1			T4	95		T5	32		T6	4
valid_sources[0x5c]	27699	1			T4	50		T5	33		T6	5
valid_sources[0x5d]	26327	1			T4	85		T5	47		T6	1
valid_sources[0x5e]	26553	1			T4	92		T5	36		T6	4
valid_sources[0x5f]	28654	1			T4	74		T5	38		T6	4
valid_sources[0x60]	29080	1			T4	60		T5	20		T6	4
valid_sources[0x61]	26914	1			T4	74		T5	40		T6	1
valid_sources[0x62]	27104	1			T4	67		T5	15		T6	5
valid_sources[0x63]	31404	1			T4	81		T5	11		T6	2
valid_sources[0x64]	27029	1			T4	74		T5	21		T6	5
valid_sources[0x65]	26472	1			T4	74		T5	15		T6	4
valid_sources[0x66]	35296	1			T4	41		T5	35		T6	2
valid_sources[0x67]	29282	1			T4	47		T5	19		T6	2
valid_sources[0x68]	28438	1			T4	64		T5	16		T6	2
valid_sources[0x69]	26410	1			T4	71		T5	19		T6	2
valid_sources[0x6a]	29017	1			T4	83		T5	26		T6	1
valid_sources[0x6b]	27545	1			T3	1		T4	42		T5	36
valid_sources[0x6c]	28514	1			T4	81		T5	20		T6	5
valid_sources[0x6d]	28089	1			T4	89		T5	19		T6	2
valid_sources[0x6e]	26360	1			T4	53		T5	26		T6	5
valid_sources[0x6f]	29445	1			T4	67		T5	20		T6	7
valid_sources[0x70]	30368	1			T4	74		T5	30		T6	1
valid_sources[0x71]	29710	1			T4	49		T5	47		T6	1
valid_sources[0x72]	28128	1			T4	41		T5	33		T6	5
valid_sources[0x73]	27202	1			T4	79		T5	31		T6	2
valid_sources[0x74]	27818	1			T4	80		T5	17		T6	4
valid_sources[0x75]	26138	1			T4	70		T5	9		T6	6
valid_sources[0x76]	27318	1			T4	58		T5	26		T6	3
valid_sources[0x77]	29766	1			T4	74		T5	7		T6	4
valid_sources[0x78]	27946	1			T4	66		T5	37		T6	2
valid_sources[0x79]	27286	1			T4	76		T5	17		T6	2
valid_sources[0x7a]	26665	1			T4	65		T5	8		T6	2
valid_sources[0x7b]	28193	1			T4	82		T5	28		T6	3
valid_sources[0x7c]	29057	1			T4	71		T5	41		T6	1
valid_sources[0x7d]	25934	1			T4	48		T5	8		T6	6
valid_sources[0x7e]	31077	1			T4	51		T5	25		T6	4
valid_sources[0x7f]	26737	1			T4	70		T5	8		T6	3
valid_sources[0x80]	28179	1			T4	53		T5	28		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

945328

1

T1

1238

T2

255

T3

1

values[0x0]

all_enables

biggest_size

1569392

1

T1

452

T2

421

T3

4

values[0x1]

all_enables

biggest_size

1547767

1

T1

461

T2

462

T4

5344