Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3347053

1

T1

1234

T2

257

T3

13

full_word

4061671

1

T1

2151

T2

1138

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7408284	1			T1	3385		T2	1395		T3	18
auto[TlIntgErrCmd]	154	1			T98	13		T99	5		T101	3
auto[TlIntgErrData]	138	1			T98	6		T99	8		T101	3
auto[TlIntgErrBoth]	148	1			T98	11		T99	7		T101	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3967879

1

T1

2461

T2

510

T3

1

auto[1]

3440845

1

T1

924

T2

885

T3

17

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3022151	1			T1	1223		T2	255		T4	2952
auto[TlIntgErrNone]	partial	auto[1]	324500	1			T1	11		T2	2		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	945539	1			T1	1238		T2	255		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3116094	1			T1	913		T2	883		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T98	6		T99	2		T101	1
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T98	5		T99	3		T101	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T162	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T98	2		T146	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T98	2		T99	4		T101	2
auto[TlIntgErrData]	partial	auto[1]	73	1			T98	2		T99	2		T101	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T98	2		T99	1		T158	3
auto[TlIntgErrData]	full_word	auto[1]	7	1			T99	1		T157	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T98	2		T99	4		T101	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T98	7		T99	3		T101	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T157	1		T160	1		T158	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T98	2		T160	2		T161	2