Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T4,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	762395087	613745281	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	762395087	3566979	0	0
GntImpliesValid_A	762395087	3566979	0	0
GrantKnown_A	762395087	613745281	0	0
IdxKnown_A	762395087	613745281	0	0
IndexIsCorrect_A	762395087	3566979	0	0
LockArbDecision_A	762395087	0	0	0
NoReadyValidNoGrant_A	762395087	0	0	0
ReadyAndValidImplyGrant_A	762395087	3566979	0	0
ReqAndReadyImplyGrant_A	762395087	3566979	0	0
ReqImpliesValid_A	762395087	3566979	0	0
ReqStaysHighUntilGranted0_M	762395087	0	0	0
RoundRobin_A	762395087	7	0	975
ValidKnown_A	762395087	613745281	0	0
gen_data_port_assertion.DataFlow_A	762395087	3566979	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	613745281	0	0
T1	339118	338235	0	0
T2	411995	411902	0	0
T3	1126	1063	0	0
T4	885508	882071	0	0
T5	644369	406093	0	0
T6	395677	278960	0	0
T7	24463	21745	0	0
T8	971714	653013	0	0
T9	2598	2536	0	0
T10	586244	356957	0	0
T11	165384	82692	0	0
T12	260712	127440	0	0
T13	836773	834833	0	0
T14	74087	73736	0	0
T15	29672	29672	0	0
T16	0	30240	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	613745281	0	0
T1	339118	338235	0	0
T2	411995	411902	0	0
T3	1126	1063	0	0
T4	885508	882071	0	0
T5	644369	406093	0	0
T6	395677	278960	0	0
T7	24463	21745	0	0
T8	971714	653013	0	0
T9	2598	2536	0	0
T10	586244	356957	0	0
T11	165384	82692	0	0
T12	260712	127440	0	0
T13	836773	834833	0	0
T14	74087	73736	0	0
T15	29672	29672	0	0
T16	0	30240	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	613745281	0	0
T1	339118	338235	0	0
T2	411995	411902	0	0
T3	1126	1063	0	0
T4	885508	882071	0	0
T5	644369	406093	0	0
T6	395677	278960	0	0
T7	24463	21745	0	0
T8	971714	653013	0	0
T9	2598	2536	0	0
T10	586244	356957	0	0
T11	165384	82692	0	0
T12	260712	127440	0	0
T13	836773	834833	0	0
T14	74087	73736	0	0
T15	29672	29672	0	0
T16	0	30240	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	7	0	975
T52	718407	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	29662	0	0	1
T60	394505	0	0	1
T61	267621	0	0	1
T62	12432	0	0	1
T63	265082	0	0	1
T64	110922	0	0	1
T65	1343	0	0	1
T66	232980	0	0	1
T67	11952	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	613745281	0	0
T1	339118	338235	0	0
T2	411995	411902	0	0
T3	1126	1063	0	0
T4	885508	882071	0	0
T5	644369	406093	0	0
T6	395677	278960	0	0
T7	24463	21745	0	0
T8	971714	653013	0	0
T9	2598	2536	0	0
T10	586244	356957	0	0
T11	165384	82692	0	0
T12	260712	127440	0	0
T13	836773	834833	0	0
T14	74087	73736	0	0
T15	29672	29672	0	0
T16	0	30240	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	762395087	3566979	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	885508	21070	0	0
T5	644369	5698	0	0
T6	395677	0	0	0
T7	24463	273	0	0
T8	971714	7014	0	0
T9	2598	832	0	0
T10	586244	9166	0	0
T11	165384	832	0	0
T12	260712	3056	0	0
T13	1673546	1555	0	0
T14	148174	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	4987	0	0
T29	0	4850	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	3452	0	0
T51	0	149	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147266944	24787494	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	147266944	574373	0	0
GntImpliesValid_A	147266944	574373	0	0
GrantKnown_A	147266944	24787494	0	0
IdxKnown_A	147266944	24787494	0	0
IndexIsCorrect_A	147266944	574373	0	0
LockArbDecision_A	147266944	0	0	0
NoReadyValidNoGrant_A	147266944	0	0	0
ReadyAndValidImplyGrant_A	147266944	574373	0	0
ReqAndReadyImplyGrant_A	147266944	574373	0	0
ReqImpliesValid_A	147266944	574373	0	0
ReqStaysHighUntilGranted0_M	147266944	0	0	0
RoundRobin_A	147266944	0	0	0
ValidKnown_A	147266944	24787494	0	0
gen_data_port_assertion.DataFlow_A	147266944	574373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	24787494	0	0
T5	231984	225744	0	0
T6	110182	103736	0	0
T7	2624	2624	0	0
T8	316800	111656	0	0
T10	225607	77320	0	0
T11	82692	0	0	0
T12	130356	127440	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	24787494	0	0
T5	231984	225744	0	0
T6	110182	103736	0	0
T7	2624	2624	0	0
T8	316800	111656	0	0
T10	225607	77320	0	0
T11	82692	0	0	0
T12	130356	127440	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	24787494	0	0
T5	231984	225744	0	0
T6	110182	103736	0	0
T7	2624	2624	0	0
T8	316800	111656	0	0
T10	225607	77320	0	0
T11	82692	0	0	0
T12	130356	127440	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	24787494	0	0
T5	231984	225744	0	0
T6	110182	103736	0	0
T7	2624	2624	0	0
T8	316800	111656	0	0
T10	225607	77320	0	0
T11	82692	0	0	0
T12	130356	127440	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	4168	0	0
T27	0	792	0	0
T28	0	167664	0	0
T29	0	159144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	574373	0	0
T5	231984	3878	0	0
T6	110182	0	0	0
T7	2624	200	0	0
T8	316800	3115	0	0
T10	225607	3270	0	0
T11	82692	0	0	0
T12	130356	2034	0	0
T13	836773	0	0	0
T14	74087	0	0	0
T15	29672	0	0	0
T17	0	155	0	0
T28	0	2693	0	0
T29	0	3544	0	0
T46	0	3323	0	0
T51	0	149	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T4,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147266944	121182218	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	147266944	764886	0	0
GntImpliesValid_A	147266944	764886	0	0
GrantKnown_A	147266944	121182218	0	0
IdxKnown_A	147266944	121182218	0	0
IndexIsCorrect_A	147266944	764886	0	0
LockArbDecision_A	147266944	0	0	0
NoReadyValidNoGrant_A	147266944	0	0	0
ReadyAndValidImplyGrant_A	147266944	764886	0	0
ReqAndReadyImplyGrant_A	147266944	764886	0	0
ReqImpliesValid_A	147266944	764886	0	0
ReqStaysHighUntilGranted0_M	147266944	0	0	0
RoundRobin_A	147266944	0	0	0
ValidKnown_A	147266944	121182218	0	0
gen_data_port_assertion.DataFlow_A	147266944	764886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	121182218	0	0
T1	262200	261392	0	0
T2	66982	66982	0	0
T4	488486	485056	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	203322	0	0
T10	225607	144630	0	0
T11	82692	82692	0	0
T12	130356	0	0	0
T13	0	834833	0	0
T14	0	73736	0	0
T15	0	29672	0	0
T16	0	30240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	121182218	0	0
T1	262200	261392	0	0
T2	66982	66982	0	0
T4	488486	485056	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	203322	0	0
T10	225607	144630	0	0
T11	82692	82692	0	0
T12	130356	0	0	0
T13	0	834833	0	0
T14	0	73736	0	0
T15	0	29672	0	0
T16	0	30240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	121182218	0	0
T1	262200	261392	0	0
T2	66982	66982	0	0
T4	488486	485056	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	203322	0	0
T10	225607	144630	0	0
T11	82692	82692	0	0
T12	130356	0	0	0
T13	0	834833	0	0
T14	0	73736	0	0
T15	0	29672	0	0
T16	0	30240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	121182218	0	0
T1	262200	261392	0	0
T2	66982	66982	0	0
T4	488486	485056	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	203322	0	0
T10	225607	144630	0	0
T11	82692	82692	0	0
T12	130356	0	0	0
T13	0	834833	0	0
T14	0	73736	0	0
T15	0	29672	0	0
T16	0	30240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147266944	764886	0	0
T4	488486	10255	0	0
T5	231984	0	0	0
T6	110182	0	0	0
T7	2624	0	0	0
T8	316800	2	0	0
T10	225607	10	0	0
T11	82692	0	0	0
T12	130356	0	0	0
T13	836773	1555	0	0
T14	74087	0	0	0
T28	0	2294	0	0
T29	0	1306	0	0
T38	0	535	0	0
T39	0	5644	0	0
T45	0	2976	0	0
T46	0	129	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	467861199	467775569	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	467861199	2227720	0	0
GntImpliesValid_A	467861199	2227720	0	0
GrantKnown_A	467861199	467775569	0	0
IdxKnown_A	467861199	467775569	0	0
IndexIsCorrect_A	467861199	2227720	0	0
LockArbDecision_A	467861199	0	0	0
NoReadyValidNoGrant_A	467861199	0	0	0
ReadyAndValidImplyGrant_A	467861199	2227720	0	0
ReqAndReadyImplyGrant_A	467861199	2227720	0	0
ReqImpliesValid_A	467861199	2227720	0	0
ReqStaysHighUntilGranted0_M	467861199	0	0	0
RoundRobin_A	467861199	7	0	975
ValidKnown_A	467861199	467775569	0	0
gen_data_port_assertion.DataFlow_A	467861199	2227720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	467775569	0	0
T1	76918	76843	0	0
T2	345013	344920	0	0
T3	1126	1063	0	0
T4	397022	397015	0	0
T5	180401	180349	0	0
T6	175313	175224	0	0
T7	19215	19121	0	0
T8	338114	338035	0	0
T9	2598	2536	0	0
T10	135030	135007	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	467775569	0	0
T1	76918	76843	0	0
T2	345013	344920	0	0
T3	1126	1063	0	0
T4	397022	397015	0	0
T5	180401	180349	0	0
T6	175313	175224	0	0
T7	19215	19121	0	0
T8	338114	338035	0	0
T9	2598	2536	0	0
T10	135030	135007	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	467775569	0	0
T1	76918	76843	0	0
T2	345013	344920	0	0
T3	1126	1063	0	0
T4	397022	397015	0	0
T5	180401	180349	0	0
T6	175313	175224	0	0
T7	19215	19121	0	0
T8	338114	338035	0	0
T9	2598	2536	0	0
T10	135030	135007	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	7	0	975
T52	718407	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	29662	0	0	1
T60	394505	0	0	1
T61	267621	0	0	1
T62	12432	0	0	1
T63	265082	0	0	1
T64	110922	0	0	1
T65	1343	0	0	1
T66	232980	0	0	1
T67	11952	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	467775569	0	0
T1	76918	76843	0	0
T2	345013	344920	0	0
T3	1126	1063	0	0
T4	397022	397015	0	0
T5	180401	180349	0	0
T6	175313	175224	0	0
T7	19215	19121	0	0
T8	338114	338035	0	0
T9	2598	2536	0	0
T10	135030	135007	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467861199	2227720	0	0
T1	76918	832	0	0
T2	345013	832	0	0
T3	1126	0	0	0
T4	397022	10815	0	0
T5	180401	1820	0	0
T6	175313	0	0	0
T7	19215	73	0	0
T8	338114	3897	0	0
T9	2598	832	0	0
T10	135030	5886	0	0
T11	0	832	0	0
T12	0	1022	0	0