Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3672426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4393678

1

T1

2970

T2

191

T3

979

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4414128	1			T1	4225		T2	1		T3	184
values[0x0]	1824740	1			T1	453		T2	124		T3	434
values[0x1]	1827236	1			T1	438		T2	100		T3	465

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2610783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5455321

1

T1

3367

T2

203

T3

995

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29987	1			T1	22		T2	2		T3	6
valid_sources[0x01]	26266	1			T1	23		T3	2		T6	45
valid_sources[0x02]	29404	1			T1	20		T3	5		T5	3
valid_sources[0x03]	30860	1			T1	16		T3	3		T5	1
valid_sources[0x04]	29765	1			T1	14		T3	4		T6	40
valid_sources[0x05]	33506	1			T1	16		T2	2		T3	3
valid_sources[0x06]	35282	1			T1	18		T3	6		T5	3
valid_sources[0x07]	30945	1			T1	20		T3	7		T5	2
valid_sources[0x08]	30896	1			T1	20		T3	2		T5	2
valid_sources[0x09]	39575	1			T1	6		T3	4		T6	36
valid_sources[0x0a]	29645	1			T1	15		T5	2		T6	40
valid_sources[0x0b]	31798	1			T1	18		T2	3		T3	3
valid_sources[0x0c]	37784	1			T1	26		T3	6		T5	1
valid_sources[0x0d]	41036	1			T1	17		T3	4		T5	8
valid_sources[0x0e]	28145	1			T1	10		T3	3		T5	4
valid_sources[0x0f]	29594	1			T1	14		T3	4		T4	1
valid_sources[0x10]	33356	1			T1	30		T2	6		T3	1
valid_sources[0x11]	27967	1			T1	19		T2	5		T3	3
valid_sources[0x12]	35030	1			T1	22		T3	4		T5	6
valid_sources[0x13]	34637	1			T1	21		T3	5		T6	80
valid_sources[0x14]	29357	1			T1	19		T2	4		T3	5
valid_sources[0x15]	29654	1			T1	17		T2	5		T3	2
valid_sources[0x16]	31070	1			T1	25		T3	5		T5	6
valid_sources[0x17]	28835	1			T1	21		T3	3		T5	7
valid_sources[0x18]	26819	1			T1	21		T3	3		T5	4
valid_sources[0x19]	30491	1			T1	27		T2	2		T3	3
valid_sources[0x1a]	31528	1			T1	9		T2	3		T3	6
valid_sources[0x1b]	31997	1			T1	17		T3	3		T5	2
valid_sources[0x1c]	28448	1			T1	18		T3	4		T5	2
valid_sources[0x1d]	30127	1			T1	18		T3	5		T5	3
valid_sources[0x1e]	31414	1			T1	20		T3	6		T5	4
valid_sources[0x1f]	28684	1			T1	20		T2	1		T3	5
valid_sources[0x20]	32788	1			T1	25		T3	5		T6	71
valid_sources[0x21]	37278	1			T1	29		T3	3		T5	9
valid_sources[0x22]	31587	1			T1	14		T2	1		T3	3
valid_sources[0x23]	29292	1			T1	22		T3	2		T5	6
valid_sources[0x24]	28473	1			T1	21		T3	7		T5	3
valid_sources[0x25]	28131	1			T1	26		T3	7		T5	3
valid_sources[0x26]	28618	1			T1	16		T2	1		T3	5
valid_sources[0x27]	32238	1			T1	24		T3	1		T5	4
valid_sources[0x28]	31404	1			T1	12		T2	3		T3	2
valid_sources[0x29]	33408	1			T1	20		T3	1		T5	1
valid_sources[0x2a]	29099	1			T1	13		T3	3		T5	5
valid_sources[0x2b]	39510	1			T1	17		T2	4		T3	4
valid_sources[0x2c]	31606	1			T1	14		T3	5		T5	4
valid_sources[0x2d]	40766	1			T1	11		T3	6		T5	6
valid_sources[0x2e]	37493	1			T1	33		T2	6		T3	2
valid_sources[0x2f]	30030	1			T1	19		T3	2		T5	4
valid_sources[0x30]	29739	1			T1	26		T2	2		T3	5
valid_sources[0x31]	28621	1			T1	26		T2	2		T3	6
valid_sources[0x32]	28891	1			T1	15		T2	2		T3	8
valid_sources[0x33]	33400	1			T1	16		T3	4		T5	9
valid_sources[0x34]	30977	1			T1	19		T3	3		T5	4
valid_sources[0x35]	33111	1			T1	11		T2	1		T3	8
valid_sources[0x36]	29797	1			T1	25		T2	3		T3	8
valid_sources[0x37]	42839	1			T1	30		T2	9		T3	5
valid_sources[0x38]	27214	1			T1	21		T3	5		T5	1
valid_sources[0x39]	35845	1			T1	15		T3	4		T5	3
valid_sources[0x3a]	37689	1			T1	21		T3	6		T5	1
valid_sources[0x3b]	29156	1			T1	26		T3	4		T5	3
valid_sources[0x3c]	33134	1			T1	18		T3	10		T5	1
valid_sources[0x3d]	32999	1			T1	17		T2	1		T3	7
valid_sources[0x3e]	29609	1			T1	22		T3	4		T5	4
valid_sources[0x3f]	29723	1			T1	11		T3	2		T5	1
valid_sources[0x40]	28835	1			T1	29		T2	1		T3	2
valid_sources[0x41]	29264	1			T1	17		T3	3		T5	3
valid_sources[0x42]	32931	1			T1	30		T3	5		T5	3
valid_sources[0x43]	37865	1			T1	20		T3	6		T5	8
valid_sources[0x44]	29904	1			T1	19		T2	2		T3	3
valid_sources[0x45]	33239	1			T1	43		T3	5		T5	2
valid_sources[0x46]	29437	1			T1	15		T3	7		T5	4
valid_sources[0x47]	29093	1			T1	11		T3	7		T5	5
valid_sources[0x48]	34201	1			T1	22		T3	2		T5	2
valid_sources[0x49]	30604	1			T1	10		T3	6		T5	9
valid_sources[0x4a]	29781	1			T1	31		T2	2		T3	3
valid_sources[0x4b]	29412	1			T1	16		T2	2		T3	4
valid_sources[0x4c]	30228	1			T1	26		T3	5		T5	1
valid_sources[0x4d]	41881	1			T1	21		T3	3		T6	46
valid_sources[0x4e]	47859	1			T1	29		T2	4		T3	4
valid_sources[0x4f]	30376	1			T1	21		T2	1		T3	1
valid_sources[0x50]	29055	1			T1	23		T3	11		T5	3
valid_sources[0x51]	30091	1			T1	30		T2	1		T3	1
valid_sources[0x52]	33340	1			T1	16		T2	1		T3	1
valid_sources[0x53]	28266	1			T1	19		T3	3		T5	6
valid_sources[0x54]	28482	1			T1	21		T3	3		T6	26
valid_sources[0x55]	28980	1			T1	20		T3	5		T5	5
valid_sources[0x56]	29984	1			T1	14		T2	2		T3	11
valid_sources[0x57]	29887	1			T1	13		T2	4		T3	3
valid_sources[0x58]	30271	1			T1	26		T3	7		T5	8
valid_sources[0x59]	28408	1			T1	21		T3	3		T5	5
valid_sources[0x5a]	32665	1			T1	21		T2	1		T3	6
valid_sources[0x5b]	28372	1			T1	19		T2	3		T3	1
valid_sources[0x5c]	29687	1			T1	23		T3	3		T5	3
valid_sources[0x5d]	29270	1			T1	37		T2	5		T3	2
valid_sources[0x5e]	31360	1			T1	15		T3	5		T5	4
valid_sources[0x5f]	36518	1			T1	17		T2	1		T3	8
valid_sources[0x60]	32618	1			T1	14		T3	2		T5	1
valid_sources[0x61]	32757	1			T1	25		T2	1		T3	7
valid_sources[0x62]	28947	1			T1	19		T3	6		T5	2
valid_sources[0x63]	32425	1			T1	26		T2	1		T3	4
valid_sources[0x64]	30766	1			T1	18		T3	3		T5	7
valid_sources[0x65]	27685	1			T1	8		T3	1		T5	5
valid_sources[0x66]	30735	1			T1	26		T3	3		T5	3
valid_sources[0x67]	32990	1			T1	31		T2	1		T3	5
valid_sources[0x68]	27978	1			T1	26		T2	2		T3	1
valid_sources[0x69]	31400	1			T1	27		T2	3		T3	6
valid_sources[0x6a]	31812	1			T1	20		T2	2		T3	3
valid_sources[0x6b]	32090	1			T1	30		T3	4		T5	2
valid_sources[0x6c]	28991	1			T1	17		T3	4		T5	4
valid_sources[0x6d]	30710	1			T1	26		T3	4		T5	5
valid_sources[0x6e]	32448	1			T1	15		T2	2		T3	3
valid_sources[0x6f]	31275	1			T1	19		T2	1		T3	4
valid_sources[0x70]	33133	1			T1	18		T3	9		T5	1
valid_sources[0x71]	31289	1			T1	23		T3	6		T5	3
valid_sources[0x72]	31028	1			T1	11		T2	1		T3	4
valid_sources[0x73]	31971	1			T1	25		T3	4		T5	6
valid_sources[0x74]	33296	1			T1	17		T3	1		T5	4
valid_sources[0x75]	31513	1			T1	27		T3	2		T5	5
valid_sources[0x76]	35329	1			T1	17		T2	1		T3	5
valid_sources[0x77]	30285	1			T1	17		T2	2		T3	7
valid_sources[0x78]	27764	1			T1	16		T2	1		T3	1
valid_sources[0x79]	30150	1			T1	12		T3	7		T5	2
valid_sources[0x7a]	33621	1			T1	11		T3	5		T5	3
valid_sources[0x7b]	31194	1			T1	26		T2	1		T3	8
valid_sources[0x7c]	28472	1			T1	13		T3	8		T5	3
valid_sources[0x7d]	29183	1			T1	21		T3	6		T6	51
valid_sources[0x7e]	29767	1			T1	17		T3	4		T5	5
valid_sources[0x7f]	30580	1			T1	15		T3	7		T5	4
valid_sources[0x80]	29227	1			T1	19		T2	5		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1091810

1

T1

2090

T2

1

T3

84

values[0x0]

all_enables

biggest_size

1662838

1

T1

450

T2

109

T3

432

values[0x1]

all_enables

biggest_size

1639030

1

T1

430

T2

81

T3

463