Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3693032

1

T1

2146

T2

34

T3

104

full_word

4392833

1

T1

2970

T2

191

T3

979

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8085475	1			T1	5116		T2	225		T3	1083
auto[TlIntgErrCmd]	142	1			T85	9		T86	3		T87	4
auto[TlIntgErrData]	133	1			T85	7		T86	2		T87	3
auto[TlIntgErrBoth]	115	1			T85	4		T86	5		T87	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4417272

1

T1

4225

T2

1

T3

184

auto[1]

3668593

1

T1

891

T2

224

T3

899

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3325079	1			T1	2135		T3	100		T4	1
auto[TlIntgErrNone]	partial	auto[1]	367595	1			T1	11		T2	34		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1092007	1			T1	2090		T2	1		T3	84
auto[TlIntgErrNone]	full_word	auto[1]	3300794	1			T1	880		T2	190		T3	895
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T85	6		T87	1		T144	3
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T85	3		T86	2		T87	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T150	1		T134	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T86	1		T151	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T85	5		T144	4		T153	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T85	2		T86	2		T87	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T144	1		T145	1		T146	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T150	1		T134	1		T148	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T85	2		T86	3		T87	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T85	2		T86	1		T87	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T86	1		T154	1		T155	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T148	1		T155	1		T156	1