Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	2991023	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	2991023	0	0
T1	113004	1663	0	0
T2	62913	0	0	0
T3	12052	1663	0	0
T4	807	0	0	0
T5	51469	832	0	0
T6	177227	12491	0	0
T7	8537	1663	0	0
T8	341948	25795	0	0
T9	566701	9152	0	0
T10	11796	832	0	0
T11	0	27445	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	3144196	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	3144196	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	832	0	0
T6	177227	36168	0	0
T7	8537	832	0	0
T8	341948	26372	0	0
T9	566701	11024	0	0
T10	11796	3865	0	0
T11	0	18304	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	207876	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	207876	0	0
T6	177227	546	0	0
T7	8537	0	0	0
T8	341948	1734	0	0
T9	566701	862	0	0
T10	11796	0	0	0
T11	741021	2632	0	0
T12	366738	0	0	0
T13	47434	0	0	0
T14	0	25	0	0
T23	1191	0	0	0
T24	2986	100	0	0
T27	0	1172	0	0
T28	0	1491	0	0
T29	0	414	0	0
T35	0	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	465110	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	465110	0	0
T6	177227	2545	0	0
T7	8537	0	0	0
T8	341948	5333	0	0
T9	566701	2512	0	0
T10	11796	0	0	0
T11	741021	2632	0	0
T12	366738	0	0	0
T13	47434	0	0	0
T14	0	25	0	0
T23	1191	0	0	0
T24	2986	467	0	0
T27	0	5391	0	0
T28	0	1491	0	0
T29	0	414	0	0
T35	0	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	6304510	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	6304510	0	0
T1	113004	4284	0	0
T2	62913	225	0	0
T3	12052	251	0	0
T4	807	3	0	0
T5	51469	130	0	0
T6	177227	3362	0	0
T7	8537	370	0	0
T8	341948	65768	0	0
T9	566701	12746	0	0
T10	11796	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450404824	13493083	0	0
DepthKnown_A	450404824	450273670	0	0
RvalidKnown_A	450404824	450273670	0	0
WreadyKnown_A	450404824	450273670	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	13493083	0	0
T1	113004	4284	0	0
T2	62913	225	0	0
T3	12052	251	0	0
T4	807	15	0	0
T5	51469	129	0	0
T6	177227	14896	0	0
T7	8537	370	0	0
T8	341948	186903	0	0
T9	566701	37415	0	0
T10	11796	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450404824	450273670	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0