Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T11
1	0	Covered	T8,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Unreachable
1	1	Covered	T8,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	755348102	600061653	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	755348102	3888007	0	0
GntImpliesValid_A	755348102	3888007	0	0
GrantKnown_A	755348102	600061653	0	0
IdxKnown_A	755348102	600061653	0	0
IndexIsCorrect_A	755348102	3888007	0	0
LockArbDecision_A	755348102	0	0	0
NoReadyValidNoGrant_A	755348102	0	0	0
ReadyAndValidImplyGrant_A	755348102	3888007	0	0
ReqAndReadyImplyGrant_A	755348102	3888007	0	0
ReqImpliesValid_A	755348102	3888007	0	0
ReqStaysHighUntilGranted0_M	755348102	0	0	0
RoundRobin_A	755348102	3	0	976
ValidKnown_A	755348102	600061653	0	0
gen_data_port_assertion.DataFlow_A	755348102	3888007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	600061653	0	0
T1	126704	126608	0	0
T2	121591	89982	0	0
T3	62356	37124	0	0
T4	807	711	0	0
T5	207619	129276	0	0
T6	1821793	996404	0	0
T7	39491	23944	0	0
T8	603366	704842	0	0
T9	1652219	1102424	0	0
T10	14956	13298	0	0
T11	319264	386756	0	0
T12	90510	90320	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	600061653	0	0
T1	126704	126608	0	0
T2	121591	89982	0	0
T3	62356	37124	0	0
T4	807	711	0	0
T5	207619	129276	0	0
T6	1821793	996404	0	0
T7	39491	23944	0	0
T8	603366	704842	0	0
T9	1652219	1102424	0	0
T10	14956	13298	0	0
T11	319264	386756	0	0
T12	90510	90320	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	600061653	0	0
T1	126704	126608	0	0
T2	121591	89982	0	0
T3	62356	37124	0	0
T4	807	711	0	0
T5	207619	129276	0	0
T6	1821793	996404	0	0
T7	39491	23944	0	0
T8	603366	704842	0	0
T9	1652219	1102424	0	0
T10	14956	13298	0	0
T11	319264	386756	0	0
T12	90510	90320	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3	0	976
T32	0	1	0	0
T42	711997	1	0	1
T43	0	1	0	0
T44	139355	0	0	1
T45	274965	0	0	1
T46	2829	0	0	1
T47	27984	0	0	1
T48	5396	0	0	1
T49	1451	0	0	1
T50	6680	0	0	1
T51	45667	0	0	1
T52	22782	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	600061653	0	0
T1	126704	126608	0	0
T2	121591	89982	0	0
T3	62356	37124	0	0
T4	807	711	0	0
T5	207619	129276	0	0
T6	1821793	996404	0	0
T7	39491	23944	0	0
T8	603366	704842	0	0
T9	1652219	1102424	0	0
T10	14956	13298	0	0
T11	319264	386756	0	0
T12	90510	90320	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755348102	3888007	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	129544	840	0	0
T6	999510	22012	0	0
T7	24014	832	0	0
T8	603366	31562	0	0
T9	1652219	14824	0	0
T10	14956	832	0	0
T11	319264	45138	0	0
T12	181020	832	0	0
T13	37180	0	0	0
T14	4640	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	7558	0	0
T28	0	11834	0	0
T29	0	2432	0	0
T30	0	4400	0	0
T35	0	4044	0	0
T39	29462	0	0	0
T40	0	3939	0	0
T41	0	516	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T11
1	0	Covered	T8,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Unreachable
1	1	Covered	T8,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T9,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153758545	34483803	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153758545	736713	0	0
GntImpliesValid_A	153758545	736713	0	0
GrantKnown_A	153758545	34483803	0	0
IdxKnown_A	153758545	34483803	0	0
IndexIsCorrect_A	153758545	736713	0	0
LockArbDecision_A	153758545	0	0	0
NoReadyValidNoGrant_A	153758545	0	0	0
ReadyAndValidImplyGrant_A	153758545	736713	0	0
ReqAndReadyImplyGrant_A	153758545	736713	0	0
ReqImpliesValid_A	153758545	736713	0	0
ReqStaysHighUntilGranted0_M	153758545	0	0	0
RoundRobin_A	153758545	0	0	0
ValidKnown_A	153758545	34483803	0	0
gen_data_port_assertion.DataFlow_A	153758545	736713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	34483803	0	0
T2	29339	27160	0	0
T3	25152	0	0	0
T5	78075	0	0	0
T6	822283	0	0	0
T7	15477	0	0	0
T8	130709	259088	0	0
T9	542759	151680	0	0
T10	1580	0	0	0
T11	159632	254232	0	0
T12	90510	0	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	34483803	0	0
T2	29339	27160	0	0
T3	25152	0	0	0
T5	78075	0	0	0
T6	822283	0	0	0
T7	15477	0	0	0
T8	130709	259088	0	0
T9	542759	151680	0	0
T10	1580	0	0	0
T11	159632	254232	0	0
T12	90510	0	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	34483803	0	0
T2	29339	27160	0	0
T3	25152	0	0	0
T5	78075	0	0	0
T6	822283	0	0	0
T7	15477	0	0	0
T8	130709	259088	0	0
T9	542759	151680	0	0
T10	1580	0	0	0
T11	159632	254232	0	0
T12	90510	0	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	34483803	0	0
T2	29339	27160	0	0
T3	25152	0	0	0
T5	78075	0	0	0
T6	822283	0	0	0
T7	15477	0	0	0
T8	130709	259088	0	0
T9	542759	151680	0	0
T10	1580	0	0	0
T11	159632	254232	0	0
T12	90510	0	0	0
T14	0	2280	0	0
T26	0	64832	0	0
T27	0	118600	0	0
T28	0	182368	0	0
T29	0	133416	0	0
T30	0	38240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	736713	0	0
T8	130709	7074	0	0
T9	542759	3478	0	0
T10	1580	0	0	0
T11	159632	10491	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	133	0	0
T16	0	3118	0	0
T25	22681	0	0	0
T26	67895	0	0	0
T27	0	5318	0	0
T28	0	6631	0	0
T29	0	2432	0	0
T30	0	1529	0	0
T39	29462	0	0	0
T40	0	3939	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153758545	117834678	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153758545	771524	0	0
GntImpliesValid_A	153758545	771524	0	0
GrantKnown_A	153758545	117834678	0	0
IdxKnown_A	153758545	117834678	0	0
IndexIsCorrect_A	153758545	771524	0	0
LockArbDecision_A	153758545	0	0	0
NoReadyValidNoGrant_A	153758545	0	0	0
ReadyAndValidImplyGrant_A	153758545	771524	0	0
ReqAndReadyImplyGrant_A	153758545	771524	0	0
ReqImpliesValid_A	153758545	771524	0	0
ReqStaysHighUntilGranted0_M	153758545	0	0	0
RoundRobin_A	153758545	0	0	0
ValidKnown_A	153758545	117834678	0	0
gen_data_port_assertion.DataFlow_A	153758545	771524	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	117834678	0	0
T1	13700	13700	0	0
T2	29339	0	0	0
T3	25152	25152	0	0
T5	78075	77886	0	0
T6	822283	819183	0	0
T7	15477	15477	0	0
T8	130709	103833	0	0
T9	542759	384251	0	0
T10	1580	1580	0	0
T11	159632	132524	0	0
T12	0	90320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	117834678	0	0
T1	13700	13700	0	0
T2	29339	0	0	0
T3	25152	25152	0	0
T5	78075	77886	0	0
T6	822283	819183	0	0
T7	15477	15477	0	0
T8	130709	103833	0	0
T9	542759	384251	0	0
T10	1580	1580	0	0
T11	159632	132524	0	0
T12	0	90320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	117834678	0	0
T1	13700	13700	0	0
T2	29339	0	0	0
T3	25152	25152	0	0
T5	78075	77886	0	0
T6	822283	819183	0	0
T7	15477	15477	0	0
T8	130709	103833	0	0
T9	542759	384251	0	0
T10	1580	1580	0	0
T11	159632	132524	0	0
T12	0	90320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	117834678	0	0
T1	13700	13700	0	0
T2	29339	0	0	0
T3	25152	25152	0	0
T5	78075	77886	0	0
T6	822283	819183	0	0
T7	15477	15477	0	0
T8	130709	103833	0	0
T9	542759	384251	0	0
T10	1580	1580	0	0
T11	159632	132524	0	0
T12	0	90320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153758545	771524	0	0
T5	78075	4	0	0
T6	822283	11440	0	0
T7	15477	0	0	0
T8	130709	4906	0	0
T9	542759	3703	0	0
T10	1580	0	0	0
T11	159632	10598	0	0
T12	90510	0	0	0
T13	18590	0	0	0
T14	2320	0	0	0
T27	0	2240	0	0
T28	0	5203	0	0
T30	0	2871	0	0
T35	0	4044	0	0
T41	0	516	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	447831012	447743172	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	447831012	2379770	0	0
GntImpliesValid_A	447831012	2379770	0	0
GrantKnown_A	447831012	447743172	0	0
IdxKnown_A	447831012	447743172	0	0
IndexIsCorrect_A	447831012	2379770	0	0
LockArbDecision_A	447831012	0	0	0
NoReadyValidNoGrant_A	447831012	0	0	0
ReadyAndValidImplyGrant_A	447831012	2379770	0	0
ReqAndReadyImplyGrant_A	447831012	2379770	0	0
ReqImpliesValid_A	447831012	2379770	0	0
ReqStaysHighUntilGranted0_M	447831012	0	0	0
RoundRobin_A	447831012	3	0	976
ValidKnown_A	447831012	447743172	0	0
gen_data_port_assertion.DataFlow_A	447831012	2379770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	447743172	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	447743172	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	447743172	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	3	0	976
T32	0	1	0	0
T42	711997	1	0	1
T43	0	1	0	0
T44	139355	0	0	1
T45	274965	0	0	1
T46	2829	0	0	1
T47	27984	0	0	1
T48	5396	0	0	1
T49	1451	0	0	1
T50	6680	0	0	1
T51	45667	0	0	1
T52	22782	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	447743172	0	0
T1	113004	112908	0	0
T2	62913	62822	0	0
T3	12052	11972	0	0
T4	807	711	0	0
T5	51469	51390	0	0
T6	177227	177221	0	0
T7	8537	8467	0	0
T8	341948	341921	0	0
T9	566701	566493	0	0
T10	11796	11718	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447831012	2379770	0	0
T1	113004	832	0	0
T2	62913	0	0	0
T3	12052	832	0	0
T4	807	0	0	0
T5	51469	836	0	0
T6	177227	10572	0	0
T7	8537	832	0	0
T8	341948	19582	0	0
T9	566701	7643	0	0
T10	11796	832	0	0
T11	0	24049	0	0
T12	0	832	0	0