Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4038141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4474803

1

T1

7

T3

906

T4

4506

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4732765	1			T1	2		T2	55		T3	38
values[0x0]	1888165	1			T1	2		T3	434		T4	1780
values[0x1]	1892014	1			T1	7		T3	467		T4	1758

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2851699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5661245

1

T1

7

T2

21

T3

915

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35293	1			T4	7		T11	68		T12	1
valid_sources[0x01]	38141	1			T4	32		T11	83		T12	1
valid_sources[0x02]	31553	1			T3	3		T4	24		T12	1
valid_sources[0x03]	29773	1			T3	2		T4	44		T11	40
valid_sources[0x04]	35852	1			T4	32		T11	151		T12	3
valid_sources[0x05]	35997	1			T3	5		T4	13		T11	138
valid_sources[0x06]	33292	1			T3	2		T4	31		T11	74
valid_sources[0x07]	32774	1			T1	1		T2	4		T4	17
valid_sources[0x08]	34607	1			T3	7		T4	32		T11	6
valid_sources[0x09]	31061	1			T3	8		T4	8		T11	393
valid_sources[0x0a]	31049	1			T3	5		T4	9		T11	76
valid_sources[0x0b]	32816	1			T4	31		T11	11		T12	5
valid_sources[0x0c]	35140	1			T4	8		T11	242		T12	2
valid_sources[0x0d]	33234	1			T1	1		T3	2		T4	1
valid_sources[0x0e]	31822	1			T3	2		T4	4		T11	87
valid_sources[0x0f]	31976	1			T3	8		T4	12		T11	70
valid_sources[0x10]	36576	1			T3	6		T4	18		T11	358
valid_sources[0x11]	30140	1			T3	3		T4	17		T11	48
valid_sources[0x12]	31118	1			T4	4		T11	12		T12	3
valid_sources[0x13]	31405	1			T4	37		T11	4		T12	3
valid_sources[0x14]	33323	1			T3	1		T4	41		T11	56
valid_sources[0x15]	30683	1			T3	11		T4	30		T11	61
valid_sources[0x16]	30504	1			T3	3		T4	16		T11	4
valid_sources[0x17]	34365	1			T1	1		T3	1		T4	26
valid_sources[0x18]	31659	1			T3	4		T4	37		T11	78
valid_sources[0x19]	35285	1			T3	13		T4	11		T11	53
valid_sources[0x1a]	34076	1			T3	7		T4	26		T5	1
valid_sources[0x1b]	34855	1			T3	3		T4	19		T11	68
valid_sources[0x1c]	32447	1			T3	12		T4	26		T11	1
valid_sources[0x1d]	32407	1			T4	8		T11	154		T12	1
valid_sources[0x1e]	32372	1			T3	11		T4	25		T5	1
valid_sources[0x1f]	32897	1			T3	5		T4	28		T11	89
valid_sources[0x20]	31491	1			T3	1		T4	6		T11	147
valid_sources[0x21]	34302	1			T4	10		T11	83		T12	1
valid_sources[0x22]	31154	1			T3	7		T4	32		T11	3
valid_sources[0x23]	32116	1			T3	5		T4	21		T11	189
valid_sources[0x24]	35076	1			T3	4		T4	15		T11	76
valid_sources[0x25]	32849	1			T3	4		T4	23		T11	71
valid_sources[0x26]	31702	1			T3	2		T4	38		T11	235
valid_sources[0x27]	31622	1			T3	2		T4	18		T11	46
valid_sources[0x28]	31237	1			T3	9		T4	18		T11	2
valid_sources[0x29]	34390	1			T3	2		T4	48		T11	31
valid_sources[0x2a]	33284	1			T3	7		T4	56		T11	44
valid_sources[0x2b]	32146	1			T3	6		T4	10		T11	2
valid_sources[0x2c]	31844	1			T3	1		T4	3		T11	88
valid_sources[0x2d]	47124	1			T3	6		T4	24		T11	46
valid_sources[0x2e]	33994	1			T3	7		T4	15		T11	87
valid_sources[0x2f]	30815	1			T3	4		T4	17		T11	38
valid_sources[0x30]	32097	1			T3	10		T4	15		T11	53
valid_sources[0x31]	34302	1			T2	1		T3	6		T4	31
valid_sources[0x32]	38270	1			T3	15		T4	23		T11	128
valid_sources[0x33]	35321	1			T4	8		T5	2		T11	8
valid_sources[0x34]	33197	1			T1	1		T3	2		T4	11
valid_sources[0x35]	31248	1			T4	33		T11	13		T12	10
valid_sources[0x36]	30941	1			T4	11		T5	1		T11	13
valid_sources[0x37]	29861	1			T3	2		T4	29		T11	1
valid_sources[0x38]	32527	1			T4	20		T11	88		T12	3
valid_sources[0x39]	33163	1			T3	6		T4	17		T11	6
valid_sources[0x3a]	33158	1			T1	1		T3	15		T4	14
valid_sources[0x3b]	32194	1			T3	5		T4	26		T11	84
valid_sources[0x3c]	33087	1			T3	5		T4	6		T11	15
valid_sources[0x3d]	30920	1			T2	5		T4	24		T11	1
valid_sources[0x3e]	32461	1			T3	9		T4	4		T11	26
valid_sources[0x3f]	33558	1			T3	15		T4	39		T11	153
valid_sources[0x40]	32716	1			T4	3		T11	115		T12	2
valid_sources[0x41]	33817	1			T3	1		T4	18		T11	3
valid_sources[0x42]	32194	1			T4	25		T11	101		T12	5
valid_sources[0x43]	30815	1			T3	3		T4	50		T11	45
valid_sources[0x44]	37783	1			T3	8		T4	12		T11	37
valid_sources[0x45]	31808	1			T3	1		T4	24		T11	2
valid_sources[0x46]	34964	1			T4	32		T11	216		T12	6
valid_sources[0x47]	34855	1			T4	9		T11	6		T12	5
valid_sources[0x48]	31356	1			T1	1		T4	13		T7	5
valid_sources[0x49]	32355	1			T3	4		T4	19		T5	2
valid_sources[0x4a]	31303	1			T3	4		T4	10		T12	2
valid_sources[0x4b]	30583	1			T3	10		T4	22		T11	39
valid_sources[0x4c]	30897	1			T3	3		T4	22		T11	63
valid_sources[0x4d]	33338	1			T3	2		T4	11		T11	52
valid_sources[0x4e]	33446	1			T4	11		T11	127		T12	4
valid_sources[0x4f]	31975	1			T3	7		T4	9		T11	281
valid_sources[0x50]	34862	1			T4	21		T11	70		T12	1
valid_sources[0x51]	32312	1			T3	11		T4	16		T11	53
valid_sources[0x52]	39651	1			T3	1		T4	25		T5	1
valid_sources[0x53]	32843	1			T3	14		T4	6		T11	11
valid_sources[0x54]	33191	1			T3	1		T4	12		T12	3
valid_sources[0x55]	36486	1			T2	2		T3	1		T4	6
valid_sources[0x56]	51273	1			T3	13		T4	15		T12	2
valid_sources[0x57]	31458	1			T2	1		T3	6		T4	21
valid_sources[0x58]	30657	1			T3	2		T4	16		T11	157
valid_sources[0x59]	32579	1			T4	4		T11	89		T12	2
valid_sources[0x5a]	32887	1			T3	8		T4	40		T11	71
valid_sources[0x5b]	34653	1			T4	30		T11	77		T12	4
valid_sources[0x5c]	31343	1			T3	2		T4	11		T11	169
valid_sources[0x5d]	33299	1			T3	4		T4	6		T11	53
valid_sources[0x5e]	30798	1			T3	2		T4	28		T11	6
valid_sources[0x5f]	32088	1			T4	59		T11	372		T12	5
valid_sources[0x60]	31590	1			T3	4		T4	10		T11	167
valid_sources[0x61]	33213	1			T3	3		T4	28		T9	20
valid_sources[0x62]	34965	1			T3	5		T4	24		T11	460
valid_sources[0x63]	33233	1			T2	1		T3	7		T4	13
valid_sources[0x64]	32677	1			T4	22		T11	215		T12	2
valid_sources[0x65]	34416	1			T3	2		T4	17		T11	19
valid_sources[0x66]	35609	1			T3	4		T4	9		T11	42
valid_sources[0x67]	31848	1			T3	6		T4	22		T11	689
valid_sources[0x68]	31746	1			T3	2		T4	15		T11	170
valid_sources[0x69]	33581	1			T3	7		T4	11		T11	100
valid_sources[0x6a]	31175	1			T3	2		T4	5		T5	2
valid_sources[0x6b]	31269	1			T2	1		T3	5		T4	8
valid_sources[0x6c]	34893	1			T2	1		T4	18		T11	1
valid_sources[0x6d]	32713	1			T4	21		T11	28		T12	1
valid_sources[0x6e]	34645	1			T3	5		T4	22		T11	125
valid_sources[0x6f]	35285	1			T3	18		T4	14		T11	165
valid_sources[0x70]	31792	1			T3	3		T4	32		T11	35
valid_sources[0x71]	33323	1			T4	48		T11	107		T12	1
valid_sources[0x72]	35368	1			T3	2		T4	18		T11	3
valid_sources[0x73]	33853	1			T3	1		T4	51		T5	2
valid_sources[0x74]	28911	1			T3	1		T4	22		T11	152
valid_sources[0x75]	32089	1			T4	52		T11	204		T12	4
valid_sources[0x76]	33435	1			T4	32		T11	321		T12	6
valid_sources[0x77]	34649	1			T3	1		T4	22		T11	190
valid_sources[0x78]	33199	1			T4	15		T11	61		T12	4
valid_sources[0x79]	34616	1			T3	2		T4	31		T11	3
valid_sources[0x7a]	32552	1			T3	6		T4	5		T8	201
valid_sources[0x7b]	30541	1			T3	3		T4	19		T11	45
valid_sources[0x7c]	45366	1			T3	1		T4	30		T11	130
valid_sources[0x7d]	31342	1			T3	2		T4	10		T11	4
valid_sources[0x7e]	34306	1			T1	3		T3	2		T4	17
valid_sources[0x7f]	30624	1			T3	9		T4	16		T11	63
valid_sources[0x80]	33219	1			T3	18		T4	5		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1068480

1

T3

9

T4

989

T5

1

values[0x0]

all_enables

biggest_size

1714372

1

T1

2

T3

433

T4

1772

values[0x1]

all_enables

biggest_size

1691951

1

T1

5

T3

464

T4

1745