Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4059286

1

T1

4

T2

55

T3

33

full_word

4473902

1

T1

7

T3

906

T4

4506

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8532838	1			T1	11		T2	55		T3	939
auto[TlIntgErrCmd]	100	1			T105	2		T106	7		T107	5
auto[TlIntgErrData]	121	1			T105	4		T106	9		T107	9
auto[TlIntgErrBoth]	129	1			T105	4		T106	4		T107	16

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4735823

1

T1

2

T2

55

T3

38

auto[1]

3797365

1

T1

9

T3

901

T4

3538

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3666985	1			T1	2		T2	55		T3	29
auto[TlIntgErrNone]	partial	auto[1]	391967	1			T1	2		T3	4		T4	21
auto[TlIntgErrNone]	full_word	auto[0]	1068678	1			T3	9		T4	989		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	3405208	1			T1	7		T3	897		T4	3517
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T105	1		T106	1		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T105	1		T106	6		T107	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T192	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T192	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	61	1			T105	2		T106	4		T107	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T105	2		T106	5		T107	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T107	1		T193	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T107	1		T118	1		T194	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T105	2		T106	2		T107	7
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T105	2		T106	2		T107	8
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T107	1		T118	1		T114	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T195	1		T196	1		-	-