Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15
1	1	Covered	T4,T11,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15
1	1	Covered	T4,T11,T15

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1451056242	2817	0	0
SrcPulseCheck_M	456981963	2817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451056242	2817	0	0
T4	109535	10	0	0
T11	0	5	0	0
T15	0	2	0	0
T16	119864	1	0	0
T17	660687	0	0	0
T18	49035	0	0	0
T19	79147	0	0	0
T25	65510	0	0	0
T26	2534	0	0	0
T27	5166	0	0	0
T28	755438	11	0	0
T36	1559	0	0	0
T38	103467	1	0	0
T39	0	15	0	0
T43	120449	7	0	0
T44	256372	10	0	0
T45	0	4	0	0
T46	0	7	0	0
T50	242105	1	0	0
T51	170866	0	0	0
T52	297778	0	0	0
T53	15612	0	0	0
T54	2058	0	0	0
T55	204749	14	0	0
T58	0	4	0	0
T74	1327	0	0	0
T101	145422	0	0	0
T128	0	7	0	0
T157	0	7	0	0
T158	0	7	0	0
T159	0	6	0	0
T160	0	7	0	0
T161	0	13	0	0
T162	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456981963	2817	0	0
T4	178602	10	0	0
T11	0	5	0	0
T15	0	2	0	0
T16	33416	1	0	0
T17	82098	0	0	0
T18	45226	0	0	0
T19	136330	0	0	0
T25	9448	0	0	0
T26	1992	0	0	0
T27	1582	0	0	0
T28	107377	11	0	0
T38	24229	1	0	0
T39	896449	15	0	0
T43	16788	7	0	0
T44	31640	10	0	0
T45	54554	4	0	0
T46	0	7	0	0
T50	58729	1	0	0
T51	33712	0	0	0
T52	146880	0	0	0
T53	12400	0	0	0
T54	432	0	0	0
T55	566348	14	0	0
T58	0	4	0	0
T101	20340	0	0	0
T128	0	7	0	0
T157	0	7	0	0
T158	0	7	0	0
T159	0	6	0	0
T160	0	7	0	0
T161	0	13	0	0
T162	0	5	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T16,T43,T44
1	0	Covered	T16,T43,T44
1	1	Covered	T43,T44,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T43,T44
1	0	Covered	T43,T44,T45
1	1	Covered	T16,T43,T44

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	483685414	176	0	0
SrcPulseCheck_M	152327321	176	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	176	0	0
T16	119864	1	0	0
T17	660687	0	0	0
T18	49035	0	0	0
T19	79147	0	0	0
T25	65510	0	0	0
T26	2534	0	0	0
T27	5166	0	0	0
T28	755438	0	0	0
T36	1559	0	0	0
T38	103467	0	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	2	0	0
T128	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	176	0	0
T16	16708	1	0	0
T17	82098	0	0	0
T18	45226	0	0	0
T19	136330	0	0	0
T25	9448	0	0	0
T26	1992	0	0	0
T27	1582	0	0	0
T28	107377	0	0	0
T38	24229	0	0	0
T39	896449	0	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	2	0	0
T128	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T43,T44,T45
1	0	Covered	T43,T44,T45
1	1	Covered	T43,T44,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T44,T45
1	0	Covered	T43,T44,T45
1	1	Covered	T43,T44,T45

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	483685414	331	0	0
SrcPulseCheck_M	152327321	331	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	331	0	0
T43	120449	5	0	0
T44	256372	5	0	0
T45	0	2	0	0
T50	242105	0	0	0
T51	170866	0	0	0
T52	297778	0	0	0
T53	15612	0	0	0
T54	2058	0	0	0
T55	204749	0	0	0
T74	1327	0	0	0
T101	145422	0	0	0
T128	0	5	0	0
T157	0	5	0	0
T158	0	5	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	331	0	0
T43	16788	5	0	0
T44	31640	5	0	0
T45	54554	2	0	0
T50	58729	0	0	0
T51	33712	0	0	0
T52	146880	0	0	0
T53	12400	0	0	0
T54	432	0	0	0
T55	566348	0	0	0
T101	20340	0	0	0
T128	0	5	0	0
T157	0	5	0	0
T158	0	5	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15
1	1	Covered	T4,T11,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15
1	1	Covered	T4,T11,T15

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	483685414	2310	0	0
SrcPulseCheck_M	152327321	2310	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2310	0	0
T4	109535	10	0	0
T5	1402	0	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	0	0	0
T9	1948	0	0	0
T10	4940	0	0	0
T11	968889	5	0	0
T12	72849	0	0	0
T13	3533	0	0	0
T15	0	2	0	0
T28	0	11	0	0
T38	0	1	0	0
T39	0	15	0	0
T46	0	7	0	0
T50	0	1	0	0
T55	0	14	0	0
T58	0	4	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	2310	0	0
T4	178602	10	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	5	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	2	0	0
T16	16708	0	0	0
T28	0	11	0	0
T38	0	1	0	0
T39	0	15	0	0
T46	0	7	0	0
T50	0	1	0	0
T55	0	14	0	0
T58	0	4	0	0