Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T25
1	0	Covered	T5,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T4,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	788340056	634573990	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	788340056	3778993	0	0
GntImpliesValid_A	788340056	3778993	0	0
GrantKnown_A	788340056	634573990	0	0
IdxKnown_A	788340056	634573990	0	0
IndexIsCorrect_A	788340056	3778993	0	0
LockArbDecision_A	788340056	0	0	0
NoReadyValidNoGrant_A	788340056	0	0	0
ReadyAndValidImplyGrant_A	788340056	3778993	0	0
ReqAndReadyImplyGrant_A	788340056	3778993	0	0
ReqImpliesValid_A	788340056	3778993	0	0
ReqStaysHighUntilGranted0_M	788340056	0	0	0
RoundRobin_A	788340056	4	0	976
ValidKnown_A	788340056	634573990	0	0
gen_data_port_assertion.DataFlow_A	788340056	3778993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	634573990	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	7288	7211	0	0
T4	288137	286892	0	0
T5	3034	2134	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	2812	2282	0	0
T10	8716	6733	0	0
T11	485358	239892	0	0
T12	19832	9888	0	0
T13	1344	672	0	0
T14	63436	31718	0	0
T15	8768	4384	0	0
T16	16708	16708	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	634573990	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	7288	7211	0	0
T4	288137	286892	0	0
T5	3034	2134	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	2812	2282	0	0
T10	8716	6733	0	0
T11	485358	239892	0	0
T12	19832	9888	0	0
T13	1344	672	0	0
T14	63436	31718	0	0
T15	8768	4384	0	0
T16	16708	16708	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	634573990	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	7288	7211	0	0
T4	288137	286892	0	0
T5	3034	2134	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	2812	2282	0	0
T10	8716	6733	0	0
T11	485358	239892	0	0
T12	19832	9888	0	0
T13	1344	672	0	0
T14	63436	31718	0	0
T15	8768	4384	0	0
T16	16708	16708	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	4	0	976
T59	217312	1	0	1
T60	0	1	0	0
T61	0	2	0	0
T62	1768	0	0	1
T63	139622	0	0	1
T64	1534	0	0	1
T65	2050	0	0	1
T66	1948	0	0	1
T67	1739	0	0	1
T68	5581	0	0	1
T69	1304	0	0	1
T70	318452	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	634573990	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	7288	7211	0	0
T4	288137	286892	0	0
T5	3034	2134	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	2812	2282	0	0
T10	8716	6733	0	0
T11	485358	239892	0	0
T12	19832	9888	0	0
T13	1344	672	0	0
T14	63436	31718	0	0
T15	8768	4384	0	0
T16	16708	16708	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788340056	3778993	0	0
T3	4872	832	0	0
T4	288137	4959	0	0
T5	3034	23	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	2812	0	0	0
T10	8716	92	0	0
T11	1454247	10290	0	0
T12	92681	832	0	0
T13	1344	57	0	0
T14	63436	832	0	0
T15	8768	840	0	0
T16	33416	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	10671	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	7495	0	0
T56	0	5578	0	0
T57	0	3139	0	0
T58	0	302	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T25
1	0	Covered	T5,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T5,T9,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152327321	26575754	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	152327321	647421	0	0
GntImpliesValid_A	152327321	647421	0	0
GrantKnown_A	152327321	26575754	0	0
IdxKnown_A	152327321	26575754	0	0
IndexIsCorrect_A	152327321	647421	0	0
LockArbDecision_A	152327321	0	0	0
NoReadyValidNoGrant_A	152327321	0	0	0
ReadyAndValidImplyGrant_A	152327321	647421	0	0
ReqAndReadyImplyGrant_A	152327321	647421	0	0
ReqImpliesValid_A	152327321	647421	0	0
ReqStaysHighUntilGranted0_M	152327321	0	0	0
RoundRobin_A	152327321	0	0	0
ValidKnown_A	152327321	26575754	0	0
gen_data_port_assertion.DataFlow_A	152327321	647421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	26575754	0	0
T5	816	816	0	0
T9	432	432	0	0
T10	1888	1888	0	0
T11	242679	60096	0	0
T12	9916	0	0	0
T13	672	672	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	26575754	0	0
T5	816	816	0	0
T9	432	432	0	0
T10	1888	1888	0	0
T11	242679	60096	0	0
T12	9916	0	0	0
T13	672	672	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	26575754	0	0
T5	816	816	0	0
T9	432	432	0	0
T10	1888	1888	0	0
T11	242679	60096	0	0
T12	9916	0	0	0
T13	672	672	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	26575754	0	0
T5	816	816	0	0
T9	432	432	0	0
T10	1888	1888	0	0
T11	242679	60096	0	0
T12	9916	0	0	0
T13	672	672	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	8872	0	0
T26	0	1992	0	0
T27	0	1008	0	0
T28	0	135096	0	0
T29	0	51216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	647421	0	0
T5	816	12	0	0
T9	432	0	0	0
T10	1888	48	0	0
T11	242679	2454	0	0
T12	9916	0	0	0
T13	672	41	0	0
T14	31718	0	0	0
T15	4384	0	0	0
T16	16708	0	0	0
T25	9448	302	0	0
T26	0	105	0	0
T28	0	6403	0	0
T55	0	2065	0	0
T56	0	5578	0	0
T57	0	3139	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T4,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T15
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152327321	124398689	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	152327321	841731	0	0
GntImpliesValid_A	152327321	841731	0	0
GrantKnown_A	152327321	124398689	0	0
IdxKnown_A	152327321	124398689	0	0
IndexIsCorrect_A	152327321	841731	0	0
LockArbDecision_A	152327321	0	0	0
NoReadyValidNoGrant_A	152327321	0	0	0
ReadyAndValidImplyGrant_A	152327321	841731	0	0
ReqAndReadyImplyGrant_A	152327321	841731	0	0
ReqImpliesValid_A	152327321	841731	0	0
ReqStaysHighUntilGranted0_M	152327321	0	0	0
RoundRobin_A	152327321	0	0	0
ValidKnown_A	152327321	124398689	0	0
gen_data_port_assertion.DataFlow_A	152327321	841731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	124398689	0	0
T3	2416	2416	0	0
T4	178602	177362	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	179796	0	0
T12	9916	9888	0	0
T13	672	0	0	0
T14	31718	31718	0	0
T15	4384	4384	0	0
T16	0	16708	0	0
T17	0	81950	0	0
T18	0	44432	0	0
T19	0	135606	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	124398689	0	0
T3	2416	2416	0	0
T4	178602	177362	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	179796	0	0
T12	9916	9888	0	0
T13	672	0	0	0
T14	31718	31718	0	0
T15	4384	4384	0	0
T16	0	16708	0	0
T17	0	81950	0	0
T18	0	44432	0	0
T19	0	135606	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	124398689	0	0
T3	2416	2416	0	0
T4	178602	177362	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	179796	0	0
T12	9916	9888	0	0
T13	672	0	0	0
T14	31718	31718	0	0
T15	4384	4384	0	0
T16	0	16708	0	0
T17	0	81950	0	0
T18	0	44432	0	0
T19	0	135606	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	124398689	0	0
T3	2416	2416	0	0
T4	178602	177362	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	179796	0	0
T12	9916	9888	0	0
T13	672	0	0	0
T14	31718	31718	0	0
T15	4384	4384	0	0
T16	0	16708	0	0
T17	0	81950	0	0
T18	0	44432	0	0
T19	0	135606	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152327321	841731	0	0
T4	178602	1297	0	0
T5	816	0	0	0
T9	432	0	0	0
T10	1888	0	0	0
T11	242679	3158	0	0
T12	9916	0	0	0
T13	672	0	0	0
T14	31718	0	0	0
T15	4384	4	0	0
T16	16708	0	0	0
T28	0	4268	0	0
T38	0	257	0	0
T39	0	13892	0	0
T46	0	3000	0	0
T50	0	2	0	0
T55	0	5430	0	0
T58	0	302	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	483685414	483599547	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	483685414	2289841	0	0
GntImpliesValid_A	483685414	2289841	0	0
GrantKnown_A	483685414	483599547	0	0
IdxKnown_A	483685414	483599547	0	0
IndexIsCorrect_A	483685414	2289841	0	0
LockArbDecision_A	483685414	0	0	0
NoReadyValidNoGrant_A	483685414	0	0	0
ReadyAndValidImplyGrant_A	483685414	2289841	0	0
ReqAndReadyImplyGrant_A	483685414	2289841	0	0
ReqImpliesValid_A	483685414	2289841	0	0
ReqStaysHighUntilGranted0_M	483685414	0	0	0
RoundRobin_A	483685414	4	0	976
ValidKnown_A	483685414	483599547	0	0
gen_data_port_assertion.DataFlow_A	483685414	2289841	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	483599547	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	4872	4795	0	0
T4	109535	109530	0	0
T5	1402	1318	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	1948	1850	0	0
T10	4940	4845	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	483599547	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	4872	4795	0	0
T4	109535	109530	0	0
T5	1402	1318	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	1948	1850	0	0
T10	4940	4845	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	483599547	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	4872	4795	0	0
T4	109535	109530	0	0
T5	1402	1318	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	1948	1850	0	0
T10	4940	4845	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	4	0	976
T59	217312	1	0	1
T60	0	1	0	0
T61	0	2	0	0
T62	1768	0	0	1
T63	139622	0	0	1
T64	1534	0	0	1
T65	2050	0	0	1
T66	1948	0	0	1
T67	1739	0	0	1
T68	5581	0	0	1
T69	1304	0	0	1
T70	318452	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	483599547	0	0
T1	1191	1126	0	0
T2	1483	1398	0	0
T3	4872	4795	0	0
T4	109535	109530	0	0
T5	1402	1318	0	0
T6	5981	4443	0	0
T7	1011	921	0	0
T8	1691	1619	0	0
T9	1948	1850	0	0
T10	4940	4845	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483685414	2289841	0	0
T3	4872	832	0	0
T4	109535	3662	0	0
T5	1402	11	0	0
T6	5981	0	0	0
T7	1011	0	0	0
T8	1691	200	0	0
T9	1948	0	0	0
T10	4940	44	0	0
T11	968889	4678	0	0
T12	72849	832	0	0
T13	0	16	0	0
T14	0	832	0	0
T15	0	836	0	0