Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2842 |
0 |
0 |
T102 |
15029 |
6 |
0 |
0 |
T103 |
19542 |
219 |
0 |
0 |
T104 |
3651 |
8 |
0 |
0 |
T105 |
26165 |
3 |
0 |
0 |
T106 |
53864 |
2 |
0 |
0 |
T107 |
93311 |
6 |
0 |
0 |
T108 |
13498 |
11 |
0 |
0 |
T111 |
9384 |
100 |
0 |
0 |
T122 |
82350 |
7 |
0 |
0 |
T125 |
10238 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2393 |
0 |
0 |
T102 |
15029 |
23 |
0 |
0 |
T107 |
93311 |
75 |
0 |
0 |
T131 |
9896 |
17 |
0 |
0 |
T138 |
41648 |
263 |
0 |
0 |
T163 |
13631 |
12 |
0 |
0 |
T164 |
33856 |
36 |
0 |
0 |
T165 |
20653 |
89 |
0 |
0 |
T166 |
234406 |
468 |
0 |
0 |
T167 |
13697 |
74 |
0 |
0 |
T168 |
12480 |
68 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2398 |
0 |
0 |
T102 |
15029 |
36 |
0 |
0 |
T107 |
93311 |
80 |
0 |
0 |
T130 |
2915 |
5 |
0 |
0 |
T131 |
9896 |
7 |
0 |
0 |
T138 |
41648 |
260 |
0 |
0 |
T156 |
7132 |
24 |
0 |
0 |
T163 |
13631 |
44 |
0 |
0 |
T164 |
33856 |
58 |
0 |
0 |
T165 |
20653 |
63 |
0 |
0 |
T166 |
234406 |
484 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2473 |
0 |
0 |
T102 |
15029 |
35 |
0 |
0 |
T107 |
93311 |
117 |
0 |
0 |
T131 |
9896 |
33 |
0 |
0 |
T138 |
41648 |
237 |
0 |
0 |
T156 |
7132 |
6 |
0 |
0 |
T163 |
13631 |
59 |
0 |
0 |
T164 |
33856 |
79 |
0 |
0 |
T165 |
20653 |
102 |
0 |
0 |
T166 |
234406 |
418 |
0 |
0 |
T167 |
13697 |
75 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
4325 |
0 |
0 |
T102 |
15029 |
138 |
0 |
0 |
T107 |
93311 |
808 |
0 |
0 |
T130 |
2915 |
6 |
0 |
0 |
T131 |
9896 |
144 |
0 |
0 |
T138 |
41648 |
272 |
0 |
0 |
T156 |
7132 |
22 |
0 |
0 |
T163 |
13631 |
48 |
0 |
0 |
T164 |
33856 |
571 |
0 |
0 |
T165 |
20653 |
12 |
0 |
0 |
T166 |
234406 |
429 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5187 |
0 |
0 |
T102 |
15029 |
165 |
0 |
0 |
T107 |
93311 |
1110 |
0 |
0 |
T130 |
2915 |
8 |
0 |
0 |
T131 |
9896 |
9 |
0 |
0 |
T138 |
41648 |
258 |
0 |
0 |
T156 |
7132 |
11 |
0 |
0 |
T163 |
13631 |
44 |
0 |
0 |
T164 |
33856 |
452 |
0 |
0 |
T165 |
20653 |
80 |
0 |
0 |
T166 |
234406 |
382 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5128 |
0 |
0 |
T102 |
15029 |
141 |
0 |
0 |
T107 |
93311 |
978 |
0 |
0 |
T130 |
2915 |
10 |
0 |
0 |
T131 |
9896 |
13 |
0 |
0 |
T138 |
41648 |
292 |
0 |
0 |
T156 |
7132 |
5 |
0 |
0 |
T163 |
13631 |
47 |
0 |
0 |
T164 |
33856 |
660 |
0 |
0 |
T165 |
20653 |
110 |
0 |
0 |
T166 |
234406 |
373 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5047 |
0 |
0 |
T102 |
15029 |
140 |
0 |
0 |
T107 |
93311 |
956 |
0 |
0 |
T131 |
9896 |
415 |
0 |
0 |
T138 |
41648 |
251 |
0 |
0 |
T156 |
7132 |
32 |
0 |
0 |
T163 |
13631 |
37 |
0 |
0 |
T164 |
33856 |
598 |
0 |
0 |
T165 |
20653 |
47 |
0 |
0 |
T166 |
234406 |
401 |
0 |
0 |
T167 |
13697 |
27 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5879 |
0 |
0 |
T102 |
15029 |
255 |
0 |
0 |
T107 |
93311 |
1058 |
0 |
0 |
T130 |
2915 |
9 |
0 |
0 |
T131 |
9896 |
139 |
0 |
0 |
T138 |
41648 |
242 |
0 |
0 |
T156 |
7132 |
23 |
0 |
0 |
T163 |
13631 |
88 |
0 |
0 |
T164 |
33856 |
1066 |
0 |
0 |
T165 |
20653 |
87 |
0 |
0 |
T166 |
234406 |
393 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
4146 |
0 |
0 |
T102 |
15029 |
132 |
0 |
0 |
T107 |
93311 |
573 |
0 |
0 |
T131 |
9896 |
269 |
0 |
0 |
T138 |
41648 |
265 |
0 |
0 |
T156 |
7132 |
6 |
0 |
0 |
T163 |
13631 |
22 |
0 |
0 |
T164 |
33856 |
360 |
0 |
0 |
T165 |
20653 |
37 |
0 |
0 |
T166 |
234406 |
441 |
0 |
0 |
T167 |
13697 |
63 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5769 |
0 |
0 |
T102 |
15029 |
261 |
0 |
0 |
T107 |
93311 |
1319 |
0 |
0 |
T131 |
9896 |
153 |
0 |
0 |
T138 |
41648 |
240 |
0 |
0 |
T156 |
7132 |
20 |
0 |
0 |
T163 |
13631 |
75 |
0 |
0 |
T164 |
33856 |
895 |
0 |
0 |
T165 |
20653 |
65 |
0 |
0 |
T166 |
234406 |
342 |
0 |
0 |
T167 |
13697 |
53 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
5527 |
0 |
0 |
T102 |
15029 |
170 |
0 |
0 |
T107 |
93311 |
1320 |
0 |
0 |
T131 |
9896 |
251 |
0 |
0 |
T138 |
41648 |
269 |
0 |
0 |
T156 |
7132 |
19 |
0 |
0 |
T163 |
13631 |
37 |
0 |
0 |
T164 |
33856 |
721 |
0 |
0 |
T165 |
20653 |
18 |
0 |
0 |
T166 |
234406 |
504 |
0 |
0 |
T167 |
13697 |
49 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3545 |
0 |
0 |
T102 |
15029 |
104 |
0 |
0 |
T107 |
93311 |
618 |
0 |
0 |
T130 |
2915 |
8 |
0 |
0 |
T131 |
9896 |
108 |
0 |
0 |
T138 |
41648 |
214 |
0 |
0 |
T156 |
7132 |
4 |
0 |
0 |
T163 |
13631 |
38 |
0 |
0 |
T164 |
33856 |
253 |
0 |
0 |
T165 |
20653 |
60 |
0 |
0 |
T166 |
234406 |
417 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3476 |
0 |
0 |
T102 |
15029 |
119 |
0 |
0 |
T107 |
93311 |
670 |
0 |
0 |
T130 |
2915 |
7 |
0 |
0 |
T131 |
9896 |
45 |
0 |
0 |
T138 |
41648 |
295 |
0 |
0 |
T156 |
7132 |
38 |
0 |
0 |
T163 |
13631 |
19 |
0 |
0 |
T164 |
33856 |
224 |
0 |
0 |
T165 |
20653 |
62 |
0 |
0 |
T166 |
234406 |
366 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3543 |
0 |
0 |
T102 |
15029 |
138 |
0 |
0 |
T107 |
93311 |
436 |
0 |
0 |
T130 |
2915 |
12 |
0 |
0 |
T131 |
9896 |
96 |
0 |
0 |
T138 |
41648 |
276 |
0 |
0 |
T156 |
7132 |
9 |
0 |
0 |
T163 |
13631 |
27 |
0 |
0 |
T164 |
33856 |
348 |
0 |
0 |
T165 |
20653 |
86 |
0 |
0 |
T166 |
234406 |
421 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3388 |
0 |
0 |
T102 |
15029 |
70 |
0 |
0 |
T107 |
93311 |
535 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
82 |
0 |
0 |
T138 |
41648 |
292 |
0 |
0 |
T156 |
7132 |
29 |
0 |
0 |
T163 |
13631 |
35 |
0 |
0 |
T164 |
33856 |
309 |
0 |
0 |
T165 |
20653 |
89 |
0 |
0 |
T166 |
234406 |
350 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3257 |
0 |
0 |
T102 |
15029 |
70 |
0 |
0 |
T107 |
93311 |
418 |
0 |
0 |
T130 |
2915 |
3 |
0 |
0 |
T131 |
9896 |
53 |
0 |
0 |
T138 |
41648 |
278 |
0 |
0 |
T156 |
7132 |
7 |
0 |
0 |
T163 |
13631 |
30 |
0 |
0 |
T164 |
33856 |
164 |
0 |
0 |
T165 |
20653 |
56 |
0 |
0 |
T166 |
234406 |
395 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3394 |
0 |
0 |
T102 |
15029 |
125 |
0 |
0 |
T107 |
93311 |
528 |
0 |
0 |
T130 |
2915 |
3 |
0 |
0 |
T131 |
9896 |
78 |
0 |
0 |
T138 |
41648 |
268 |
0 |
0 |
T156 |
7132 |
17 |
0 |
0 |
T163 |
13631 |
68 |
0 |
0 |
T164 |
33856 |
222 |
0 |
0 |
T165 |
20653 |
97 |
0 |
0 |
T166 |
234406 |
399 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3422 |
0 |
0 |
T102 |
15029 |
122 |
0 |
0 |
T107 |
93311 |
534 |
0 |
0 |
T131 |
9896 |
38 |
0 |
0 |
T138 |
41648 |
306 |
0 |
0 |
T156 |
7132 |
40 |
0 |
0 |
T163 |
13631 |
54 |
0 |
0 |
T164 |
33856 |
309 |
0 |
0 |
T165 |
20653 |
43 |
0 |
0 |
T166 |
234406 |
421 |
0 |
0 |
T167 |
13697 |
11 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3539 |
0 |
0 |
T102 |
15029 |
88 |
0 |
0 |
T107 |
93311 |
448 |
0 |
0 |
T131 |
9896 |
115 |
0 |
0 |
T138 |
41648 |
260 |
0 |
0 |
T156 |
7132 |
30 |
0 |
0 |
T163 |
13631 |
65 |
0 |
0 |
T164 |
33856 |
396 |
0 |
0 |
T165 |
20653 |
37 |
0 |
0 |
T166 |
234406 |
425 |
0 |
0 |
T167 |
13697 |
35 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3320 |
0 |
0 |
T102 |
15029 |
157 |
0 |
0 |
T107 |
93311 |
418 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
57 |
0 |
0 |
T138 |
41648 |
314 |
0 |
0 |
T156 |
7132 |
20 |
0 |
0 |
T163 |
13631 |
20 |
0 |
0 |
T164 |
33856 |
314 |
0 |
0 |
T165 |
20653 |
38 |
0 |
0 |
T166 |
234406 |
418 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3377 |
0 |
0 |
T102 |
15029 |
121 |
0 |
0 |
T107 |
93311 |
526 |
0 |
0 |
T130 |
2915 |
7 |
0 |
0 |
T131 |
9896 |
10 |
0 |
0 |
T138 |
41648 |
232 |
0 |
0 |
T156 |
7132 |
16 |
0 |
0 |
T163 |
13631 |
47 |
0 |
0 |
T164 |
33856 |
208 |
0 |
0 |
T165 |
20653 |
61 |
0 |
0 |
T166 |
234406 |
388 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3442 |
0 |
0 |
T102 |
15029 |
132 |
0 |
0 |
T107 |
93311 |
424 |
0 |
0 |
T131 |
9896 |
119 |
0 |
0 |
T138 |
41648 |
292 |
0 |
0 |
T156 |
7132 |
53 |
0 |
0 |
T163 |
13631 |
54 |
0 |
0 |
T164 |
33856 |
206 |
0 |
0 |
T165 |
20653 |
90 |
0 |
0 |
T166 |
234406 |
378 |
0 |
0 |
T167 |
13697 |
36 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3245 |
0 |
0 |
T102 |
15029 |
57 |
0 |
0 |
T107 |
93311 |
443 |
0 |
0 |
T131 |
9896 |
64 |
0 |
0 |
T138 |
41648 |
257 |
0 |
0 |
T156 |
7132 |
45 |
0 |
0 |
T163 |
13631 |
62 |
0 |
0 |
T164 |
33856 |
240 |
0 |
0 |
T165 |
20653 |
78 |
0 |
0 |
T166 |
234406 |
377 |
0 |
0 |
T167 |
13697 |
104 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3256 |
0 |
0 |
T102 |
15029 |
102 |
0 |
0 |
T107 |
93311 |
364 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
91 |
0 |
0 |
T138 |
41648 |
212 |
0 |
0 |
T156 |
7132 |
6 |
0 |
0 |
T163 |
13631 |
63 |
0 |
0 |
T164 |
33856 |
337 |
0 |
0 |
T165 |
20653 |
76 |
0 |
0 |
T166 |
234406 |
417 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3828 |
0 |
0 |
T102 |
15029 |
150 |
0 |
0 |
T107 |
93311 |
634 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
48 |
0 |
0 |
T138 |
41648 |
235 |
0 |
0 |
T156 |
7132 |
27 |
0 |
0 |
T163 |
13631 |
67 |
0 |
0 |
T164 |
33856 |
300 |
0 |
0 |
T165 |
20653 |
90 |
0 |
0 |
T166 |
234406 |
386 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3353 |
0 |
0 |
T102 |
15029 |
81 |
0 |
0 |
T107 |
93311 |
440 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
41 |
0 |
0 |
T138 |
41648 |
271 |
0 |
0 |
T156 |
7132 |
49 |
0 |
0 |
T163 |
13631 |
63 |
0 |
0 |
T164 |
33856 |
303 |
0 |
0 |
T165 |
20653 |
82 |
0 |
0 |
T166 |
234406 |
409 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3416 |
0 |
0 |
T102 |
15029 |
126 |
0 |
0 |
T107 |
93311 |
518 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
44 |
0 |
0 |
T138 |
41648 |
271 |
0 |
0 |
T156 |
7132 |
37 |
0 |
0 |
T163 |
13631 |
58 |
0 |
0 |
T164 |
33856 |
152 |
0 |
0 |
T165 |
20653 |
44 |
0 |
0 |
T166 |
234406 |
440 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3479 |
0 |
0 |
T102 |
15029 |
103 |
0 |
0 |
T107 |
93311 |
547 |
0 |
0 |
T130 |
2915 |
6 |
0 |
0 |
T131 |
9896 |
95 |
0 |
0 |
T138 |
41648 |
267 |
0 |
0 |
T156 |
7132 |
10 |
0 |
0 |
T163 |
13631 |
30 |
0 |
0 |
T164 |
33856 |
329 |
0 |
0 |
T165 |
20653 |
64 |
0 |
0 |
T166 |
234406 |
404 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3469 |
0 |
0 |
T102 |
15029 |
139 |
0 |
0 |
T107 |
93311 |
480 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
142 |
0 |
0 |
T138 |
41648 |
264 |
0 |
0 |
T156 |
7132 |
50 |
0 |
0 |
T163 |
13631 |
47 |
0 |
0 |
T164 |
33856 |
219 |
0 |
0 |
T165 |
20653 |
38 |
0 |
0 |
T166 |
234406 |
428 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3207 |
0 |
0 |
T102 |
15029 |
133 |
0 |
0 |
T107 |
93311 |
459 |
0 |
0 |
T131 |
9896 |
41 |
0 |
0 |
T138 |
41648 |
231 |
0 |
0 |
T156 |
7132 |
14 |
0 |
0 |
T163 |
13631 |
26 |
0 |
0 |
T164 |
33856 |
128 |
0 |
0 |
T165 |
20653 |
91 |
0 |
0 |
T166 |
234406 |
407 |
0 |
0 |
T167 |
13697 |
76 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3365 |
0 |
0 |
T102 |
15029 |
20 |
0 |
0 |
T107 |
93311 |
405 |
0 |
0 |
T130 |
2915 |
1 |
0 |
0 |
T131 |
9896 |
117 |
0 |
0 |
T138 |
41648 |
247 |
0 |
0 |
T156 |
7132 |
9 |
0 |
0 |
T163 |
13631 |
14 |
0 |
0 |
T164 |
33856 |
350 |
0 |
0 |
T165 |
20653 |
128 |
0 |
0 |
T166 |
234406 |
302 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3525 |
0 |
0 |
T102 |
15029 |
131 |
0 |
0 |
T107 |
93311 |
531 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
128 |
0 |
0 |
T138 |
41648 |
263 |
0 |
0 |
T156 |
7132 |
5 |
0 |
0 |
T163 |
13631 |
80 |
0 |
0 |
T164 |
33856 |
278 |
0 |
0 |
T165 |
20653 |
56 |
0 |
0 |
T166 |
234406 |
493 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3474 |
0 |
0 |
T102 |
15029 |
132 |
0 |
0 |
T107 |
93311 |
509 |
0 |
0 |
T130 |
2915 |
3 |
0 |
0 |
T131 |
9896 |
61 |
0 |
0 |
T138 |
41648 |
269 |
0 |
0 |
T156 |
7132 |
52 |
0 |
0 |
T163 |
13631 |
47 |
0 |
0 |
T164 |
33856 |
168 |
0 |
0 |
T165 |
20653 |
64 |
0 |
0 |
T166 |
234406 |
410 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3607 |
0 |
0 |
T102 |
15029 |
75 |
0 |
0 |
T107 |
93311 |
560 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
46 |
0 |
0 |
T138 |
41648 |
313 |
0 |
0 |
T156 |
7132 |
6 |
0 |
0 |
T163 |
13631 |
72 |
0 |
0 |
T164 |
33856 |
323 |
0 |
0 |
T165 |
20653 |
53 |
0 |
0 |
T166 |
234406 |
360 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3261 |
0 |
0 |
T102 |
15029 |
68 |
0 |
0 |
T107 |
93311 |
406 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
111 |
0 |
0 |
T138 |
41648 |
259 |
0 |
0 |
T156 |
7132 |
16 |
0 |
0 |
T163 |
13631 |
95 |
0 |
0 |
T164 |
33856 |
191 |
0 |
0 |
T165 |
20653 |
68 |
0 |
0 |
T166 |
234406 |
452 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2368 |
0 |
0 |
T102 |
15029 |
38 |
0 |
0 |
T107 |
93311 |
103 |
0 |
0 |
T130 |
2915 |
7 |
0 |
0 |
T131 |
9896 |
19 |
0 |
0 |
T138 |
41648 |
223 |
0 |
0 |
T156 |
7132 |
15 |
0 |
0 |
T163 |
13631 |
42 |
0 |
0 |
T164 |
33856 |
70 |
0 |
0 |
T165 |
20653 |
102 |
0 |
0 |
T166 |
234406 |
360 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2392 |
0 |
0 |
T102 |
15029 |
36 |
0 |
0 |
T107 |
93311 |
82 |
0 |
0 |
T130 |
2915 |
5 |
0 |
0 |
T131 |
9896 |
22 |
0 |
0 |
T138 |
41648 |
293 |
0 |
0 |
T156 |
7132 |
35 |
0 |
0 |
T163 |
13631 |
52 |
0 |
0 |
T164 |
33856 |
52 |
0 |
0 |
T165 |
20653 |
70 |
0 |
0 |
T166 |
234406 |
371 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2302 |
0 |
0 |
T102 |
15029 |
18 |
0 |
0 |
T107 |
93311 |
101 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
18 |
0 |
0 |
T138 |
41648 |
223 |
0 |
0 |
T156 |
7132 |
25 |
0 |
0 |
T163 |
13631 |
61 |
0 |
0 |
T164 |
33856 |
41 |
0 |
0 |
T165 |
20653 |
86 |
0 |
0 |
T166 |
234406 |
396 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2181 |
0 |
0 |
T102 |
15029 |
25 |
0 |
0 |
T107 |
93311 |
86 |
0 |
0 |
T130 |
2915 |
11 |
0 |
0 |
T131 |
9896 |
19 |
0 |
0 |
T138 |
41648 |
254 |
0 |
0 |
T156 |
7132 |
6 |
0 |
0 |
T163 |
13631 |
56 |
0 |
0 |
T164 |
33856 |
40 |
0 |
0 |
T165 |
20653 |
71 |
0 |
0 |
T166 |
234406 |
348 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2384 |
0 |
0 |
T102 |
15029 |
19 |
0 |
0 |
T107 |
93311 |
136 |
0 |
0 |
T130 |
2915 |
10 |
0 |
0 |
T131 |
9896 |
18 |
0 |
0 |
T138 |
41648 |
288 |
0 |
0 |
T156 |
7132 |
21 |
0 |
0 |
T163 |
13631 |
45 |
0 |
0 |
T164 |
33856 |
116 |
0 |
0 |
T165 |
20653 |
47 |
0 |
0 |
T166 |
234406 |
365 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
3954 |
0 |
0 |
T24 |
6865 |
36 |
0 |
0 |
T30 |
0 |
32 |
0 |
0 |
T32 |
0 |
59 |
0 |
0 |
T33 |
0 |
39 |
0 |
0 |
T42 |
306719 |
0 |
0 |
0 |
T169 |
0 |
24 |
0 |
0 |
T170 |
0 |
14 |
0 |
0 |
T171 |
0 |
26 |
0 |
0 |
T172 |
0 |
56 |
0 |
0 |
T173 |
0 |
2 |
0 |
0 |
T174 |
0 |
30 |
0 |
0 |
T175 |
90253 |
0 |
0 |
0 |
T176 |
795 |
0 |
0 |
0 |
T177 |
65376 |
0 |
0 |
0 |
T178 |
1017 |
0 |
0 |
0 |
T179 |
1849 |
0 |
0 |
0 |
T180 |
2675 |
0 |
0 |
0 |
T181 |
607421 |
0 |
0 |
0 |
T182 |
19347 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2389 |
0 |
0 |
T102 |
15029 |
40 |
0 |
0 |
T107 |
93311 |
99 |
0 |
0 |
T131 |
9896 |
22 |
0 |
0 |
T138 |
41648 |
291 |
0 |
0 |
T156 |
7132 |
50 |
0 |
0 |
T163 |
13631 |
44 |
0 |
0 |
T164 |
33856 |
43 |
0 |
0 |
T165 |
20653 |
61 |
0 |
0 |
T166 |
234406 |
402 |
0 |
0 |
T167 |
13697 |
7 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2372 |
0 |
0 |
T102 |
15029 |
35 |
0 |
0 |
T107 |
93311 |
97 |
0 |
0 |
T130 |
2915 |
7 |
0 |
0 |
T131 |
9896 |
24 |
0 |
0 |
T138 |
41648 |
280 |
0 |
0 |
T156 |
7132 |
24 |
0 |
0 |
T163 |
13631 |
36 |
0 |
0 |
T164 |
33856 |
38 |
0 |
0 |
T165 |
20653 |
83 |
0 |
0 |
T166 |
234406 |
409 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2139 |
0 |
0 |
T102 |
15029 |
21 |
0 |
0 |
T107 |
93311 |
69 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
17 |
0 |
0 |
T138 |
41648 |
241 |
0 |
0 |
T156 |
7132 |
17 |
0 |
0 |
T163 |
13631 |
51 |
0 |
0 |
T164 |
33856 |
49 |
0 |
0 |
T165 |
20653 |
55 |
0 |
0 |
T166 |
234406 |
383 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2315 |
0 |
0 |
T102 |
15029 |
22 |
0 |
0 |
T107 |
93311 |
81 |
0 |
0 |
T131 |
9896 |
17 |
0 |
0 |
T138 |
41648 |
270 |
0 |
0 |
T156 |
7132 |
20 |
0 |
0 |
T163 |
13631 |
48 |
0 |
0 |
T164 |
33856 |
32 |
0 |
0 |
T165 |
20653 |
31 |
0 |
0 |
T166 |
234406 |
372 |
0 |
0 |
T167 |
13697 |
59 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2292 |
0 |
0 |
T102 |
15029 |
34 |
0 |
0 |
T107 |
93311 |
67 |
0 |
0 |
T131 |
9896 |
9 |
0 |
0 |
T138 |
41648 |
244 |
0 |
0 |
T156 |
7132 |
32 |
0 |
0 |
T163 |
13631 |
19 |
0 |
0 |
T164 |
33856 |
53 |
0 |
0 |
T165 |
20653 |
101 |
0 |
0 |
T166 |
234406 |
388 |
0 |
0 |
T167 |
13697 |
21 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2272 |
0 |
0 |
T102 |
15029 |
12 |
0 |
0 |
T107 |
93311 |
66 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
12 |
0 |
0 |
T138 |
41648 |
284 |
0 |
0 |
T156 |
7132 |
20 |
0 |
0 |
T163 |
13631 |
74 |
0 |
0 |
T164 |
33856 |
29 |
0 |
0 |
T165 |
20653 |
58 |
0 |
0 |
T166 |
234406 |
394 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2445 |
0 |
0 |
T102 |
15029 |
49 |
0 |
0 |
T107 |
93311 |
117 |
0 |
0 |
T131 |
9896 |
29 |
0 |
0 |
T138 |
41648 |
202 |
0 |
0 |
T163 |
13631 |
86 |
0 |
0 |
T164 |
33856 |
110 |
0 |
0 |
T165 |
20653 |
34 |
0 |
0 |
T166 |
234406 |
445 |
0 |
0 |
T167 |
13697 |
62 |
0 |
0 |
T168 |
12480 |
12 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2266 |
0 |
0 |
T102 |
15029 |
23 |
0 |
0 |
T107 |
93311 |
61 |
0 |
0 |
T130 |
2915 |
4 |
0 |
0 |
T131 |
9896 |
10 |
0 |
0 |
T138 |
41648 |
252 |
0 |
0 |
T156 |
7132 |
24 |
0 |
0 |
T163 |
13631 |
38 |
0 |
0 |
T164 |
33856 |
29 |
0 |
0 |
T165 |
20653 |
71 |
0 |
0 |
T166 |
234406 |
346 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2698 |
0 |
0 |
T102 |
15029 |
59 |
0 |
0 |
T107 |
93311 |
180 |
0 |
0 |
T131 |
9896 |
39 |
0 |
0 |
T138 |
41648 |
258 |
0 |
0 |
T156 |
7132 |
26 |
0 |
0 |
T163 |
13631 |
55 |
0 |
0 |
T164 |
33856 |
84 |
0 |
0 |
T165 |
20653 |
72 |
0 |
0 |
T166 |
234406 |
373 |
0 |
0 |
T167 |
13697 |
50 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2214 |
0 |
0 |
T102 |
15029 |
20 |
0 |
0 |
T107 |
93311 |
63 |
0 |
0 |
T130 |
2915 |
9 |
0 |
0 |
T131 |
9896 |
9 |
0 |
0 |
T138 |
41648 |
278 |
0 |
0 |
T156 |
7132 |
14 |
0 |
0 |
T163 |
13631 |
23 |
0 |
0 |
T164 |
33856 |
52 |
0 |
0 |
T165 |
20653 |
77 |
0 |
0 |
T166 |
234406 |
405 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2305 |
0 |
0 |
T102 |
15029 |
25 |
0 |
0 |
T107 |
93311 |
72 |
0 |
0 |
T131 |
9896 |
10 |
0 |
0 |
T138 |
41648 |
269 |
0 |
0 |
T156 |
7132 |
32 |
0 |
0 |
T163 |
13631 |
33 |
0 |
0 |
T164 |
33856 |
31 |
0 |
0 |
T165 |
20653 |
42 |
0 |
0 |
T166 |
234406 |
410 |
0 |
0 |
T167 |
13697 |
23 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2331 |
0 |
0 |
T102 |
15029 |
21 |
0 |
0 |
T107 |
93311 |
52 |
0 |
0 |
T131 |
9896 |
19 |
0 |
0 |
T138 |
41648 |
279 |
0 |
0 |
T156 |
7132 |
42 |
0 |
0 |
T163 |
13631 |
33 |
0 |
0 |
T164 |
33856 |
49 |
0 |
0 |
T165 |
20653 |
49 |
0 |
0 |
T166 |
234406 |
457 |
0 |
0 |
T167 |
13697 |
36 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2391 |
0 |
0 |
T102 |
15029 |
19 |
0 |
0 |
T107 |
93311 |
70 |
0 |
0 |
T130 |
2915 |
5 |
0 |
0 |
T131 |
9896 |
19 |
0 |
0 |
T138 |
41648 |
250 |
0 |
0 |
T156 |
7132 |
47 |
0 |
0 |
T163 |
13631 |
77 |
0 |
0 |
T164 |
33856 |
31 |
0 |
0 |
T165 |
20653 |
52 |
0 |
0 |
T166 |
234406 |
425 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2268 |
0 |
0 |
T102 |
15029 |
27 |
0 |
0 |
T107 |
93311 |
66 |
0 |
0 |
T130 |
2915 |
6 |
0 |
0 |
T131 |
9896 |
9 |
0 |
0 |
T138 |
41648 |
263 |
0 |
0 |
T156 |
7132 |
4 |
0 |
0 |
T163 |
13631 |
24 |
0 |
0 |
T164 |
33856 |
35 |
0 |
0 |
T165 |
20653 |
86 |
0 |
0 |
T166 |
234406 |
421 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2298 |
0 |
0 |
T102 |
15029 |
18 |
0 |
0 |
T107 |
93311 |
70 |
0 |
0 |
T130 |
2915 |
7 |
0 |
0 |
T131 |
9896 |
17 |
0 |
0 |
T138 |
41648 |
228 |
0 |
0 |
T156 |
7132 |
41 |
0 |
0 |
T163 |
13631 |
10 |
0 |
0 |
T164 |
33856 |
34 |
0 |
0 |
T165 |
20653 |
26 |
0 |
0 |
T166 |
234406 |
459 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486277153 |
2386 |
0 |
0 |
T102 |
15029 |
6 |
0 |
0 |
T107 |
93311 |
36 |
0 |
0 |
T130 |
2915 |
2 |
0 |
0 |
T131 |
9896 |
25 |
0 |
0 |
T138 |
41648 |
232 |
0 |
0 |
T156 |
7132 |
59 |
0 |
0 |
T163 |
13631 |
66 |
0 |
0 |
T164 |
33856 |
48 |
0 |
0 |
T165 |
20653 |
95 |
0 |
0 |
T166 |
234406 |
425 |
0 |
0 |