Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3907026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4493030

1

T1

1

T2

3643

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4755508	1			T1	1		T2	6894		T3	81
values[0x0]	1821570	1			T2	1811		T4	3		T5	3
values[0x1]	1822978	1			T2	1901		T4	1		T5	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2777642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5622414

1

T1

1

T2

5924

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30833	1			T2	50		T8	6		T10	3
valid_sources[0x01]	31491	1			T2	47		T8	3		T10	1
valid_sources[0x02]	32957	1			T2	40		T8	4		T10	1
valid_sources[0x03]	44307	1			T2	40		T8	1		T10	6
valid_sources[0x04]	33638	1			T2	36		T8	5		T10	1
valid_sources[0x05]	31477	1			T2	53		T8	7		T41	2
valid_sources[0x06]	31822	1			T2	39		T8	1		T10	11
valid_sources[0x07]	31758	1			T2	42		T3	1		T10	2
valid_sources[0x08]	30821	1			T2	40		T8	1		T11	1
valid_sources[0x09]	29966	1			T2	40		T8	5		T10	7
valid_sources[0x0a]	30340	1			T2	50		T8	3		T41	1
valid_sources[0x0b]	28870	1			T2	39		T3	1		T8	2
valid_sources[0x0c]	31474	1			T2	37		T8	3		T39	3
valid_sources[0x0d]	39119	1			T2	48		T8	5		T26	1
valid_sources[0x0e]	29009	1			T2	35		T8	3		T41	1
valid_sources[0x0f]	37487	1			T2	33		T3	1		T8	1
valid_sources[0x10]	38113	1			T2	43		T8	2		T11	1
valid_sources[0x11]	30489	1			T2	44		T3	2		T8	5
valid_sources[0x12]	27900	1			T2	45		T8	1		T10	2
valid_sources[0x13]	30116	1			T2	41		T8	2		T10	3
valid_sources[0x14]	30495	1			T2	52		T8	6		T10	2
valid_sources[0x15]	29024	1			T2	37		T8	1		T11	1
valid_sources[0x16]	28204	1			T2	37		T8	5		T11	1
valid_sources[0x17]	30787	1			T2	40		T8	5		T41	1
valid_sources[0x18]	36295	1			T2	45		T8	6		T10	10
valid_sources[0x19]	30626	1			T2	33		T8	3		T10	6
valid_sources[0x1a]	35322	1			T2	35		T8	9		T39	6
valid_sources[0x1b]	28616	1			T2	55		T8	3		T39	6
valid_sources[0x1c]	28336	1			T2	41		T8	2		T41	3
valid_sources[0x1d]	27978	1			T2	37		T8	5		T41	1
valid_sources[0x1e]	54242	1			T2	31		T7	875		T8	1
valid_sources[0x1f]	30012	1			T2	50		T10	1		T11	1
valid_sources[0x20]	36501	1			T2	48		T8	3		T39	4
valid_sources[0x21]	30228	1			T2	53		T3	1		T8	4
valid_sources[0x22]	33220	1			T2	45		T8	2		T10	1
valid_sources[0x23]	31384	1			T2	36		T3	2		T8	3
valid_sources[0x24]	29782	1			T2	49		T8	5		T10	3
valid_sources[0x25]	30092	1			T2	51		T8	5		T10	1
valid_sources[0x26]	30336	1			T2	38		T8	1		T10	6
valid_sources[0x27]	31311	1			T2	45		T3	1		T8	4
valid_sources[0x28]	33354	1			T2	32		T8	6		T11	2
valid_sources[0x29]	33202	1			T2	43		T8	9		T41	4
valid_sources[0x2a]	37788	1			T2	46		T3	2		T8	1
valid_sources[0x2b]	37356	1			T2	38		T8	1		T41	2
valid_sources[0x2c]	33180	1			T2	40		T5	2		T8	8
valid_sources[0x2d]	30283	1			T2	50		T8	7		T10	7
valid_sources[0x2e]	31605	1			T2	29		T8	5		T10	23
valid_sources[0x2f]	39169	1			T2	44		T8	1		T11	1
valid_sources[0x30]	33263	1			T2	52		T8	2		T41	2
valid_sources[0x31]	30079	1			T2	50		T8	2		T10	5
valid_sources[0x32]	33726	1			T2	36		T8	4		T41	1
valid_sources[0x33]	40053	1			T2	46		T8	3		T10	10
valid_sources[0x34]	33661	1			T2	30		T3	2		T8	3
valid_sources[0x35]	28730	1			T2	53		T8	5		T10	4
valid_sources[0x36]	30313	1			T2	40		T8	5		T11	2
valid_sources[0x37]	29308	1			T2	40		T8	6		T10	6
valid_sources[0x38]	29645	1			T2	53		T8	4		T10	4
valid_sources[0x39]	30901	1			T2	42		T8	1		T10	5
valid_sources[0x3a]	31496	1			T2	44		T8	2		T10	2
valid_sources[0x3b]	32939	1			T2	44		T8	3		T39	1
valid_sources[0x3c]	30606	1			T2	36		T8	5		T11	1
valid_sources[0x3d]	30897	1			T2	36		T8	2		T10	20
valid_sources[0x3e]	32652	1			T2	60		T8	2		T10	11
valid_sources[0x3f]	30916	1			T2	36		T8	6		T11	1
valid_sources[0x40]	30815	1			T2	37		T8	5		T10	4
valid_sources[0x41]	31217	1			T2	45		T8	4		T41	2
valid_sources[0x42]	32112	1			T2	32		T8	3		T41	3
valid_sources[0x43]	31233	1			T2	44		T3	1		T8	4
valid_sources[0x44]	31985	1			T2	49		T8	5		T11	1
valid_sources[0x45]	33937	1			T2	43		T8	3		T10	9
valid_sources[0x46]	29350	1			T2	40		T3	5		T8	4
valid_sources[0x47]	31789	1			T2	48		T8	5		T39	2
valid_sources[0x48]	26957	1			T2	39		T41	2		T39	4
valid_sources[0x49]	31504	1			T2	36		T5	3		T8	4
valid_sources[0x4a]	31982	1			T2	25		T8	2		T10	14
valid_sources[0x4b]	31064	1			T2	32		T8	2		T14	8
valid_sources[0x4c]	29401	1			T2	52		T8	3		T10	9
valid_sources[0x4d]	29589	1			T2	33		T8	2		T41	1
valid_sources[0x4e]	30812	1			T2	39		T8	5		T14	3
valid_sources[0x4f]	30000	1			T2	41		T8	2		T10	2
valid_sources[0x50]	38559	1			T2	34		T8	7		T10	4
valid_sources[0x51]	30223	1			T2	39		T8	7		T10	4
valid_sources[0x52]	33304	1			T2	47		T8	3		T10	6
valid_sources[0x53]	38034	1			T2	51		T3	1		T8	3
valid_sources[0x54]	29433	1			T2	42		T8	1		T41	1
valid_sources[0x55]	28205	1			T2	40		T3	2		T8	10
valid_sources[0x56]	27931	1			T2	45		T8	7		T11	1
valid_sources[0x57]	34653	1			T2	42		T8	4		T10	1
valid_sources[0x58]	29412	1			T2	45		T8	2		T39	3
valid_sources[0x59]	30481	1			T2	47		T8	2		T11	1
valid_sources[0x5a]	29793	1			T2	35		T8	6		T41	1
valid_sources[0x5b]	30660	1			T2	40		T8	1		T39	5
valid_sources[0x5c]	32579	1			T2	44		T8	5		T10	4
valid_sources[0x5d]	31578	1			T2	49		T8	1		T41	2
valid_sources[0x5e]	28758	1			T2	27		T8	3		T10	1
valid_sources[0x5f]	33750	1			T2	52		T8	4		T10	11
valid_sources[0x60]	30861	1			T2	38		T8	1		T10	7
valid_sources[0x61]	33190	1			T2	39		T8	1		T41	1
valid_sources[0x62]	34437	1			T2	37		T8	3		T10	1
valid_sources[0x63]	30643	1			T2	32		T41	3		T39	2
valid_sources[0x64]	30017	1			T2	35		T8	6		T10	6
valid_sources[0x65]	36816	1			T2	42		T8	6		T10	3
valid_sources[0x66]	30327	1			T2	61		T8	4		T10	2
valid_sources[0x67]	27809	1			T2	34		T8	3		T39	6
valid_sources[0x68]	32028	1			T2	40		T8	5		T10	7
valid_sources[0x69]	28709	1			T2	49		T8	4		T10	14
valid_sources[0x6a]	30234	1			T2	38		T8	2		T10	15
valid_sources[0x6b]	32502	1			T2	40		T8	4		T10	2
valid_sources[0x6c]	30154	1			T2	50		T39	6		T14	2
valid_sources[0x6d]	31823	1			T2	49		T3	2		T8	2
valid_sources[0x6e]	32204	1			T2	41		T8	9		T10	13
valid_sources[0x6f]	28690	1			T2	32		T3	1		T8	4
valid_sources[0x70]	29969	1			T2	37		T8	6		T41	1
valid_sources[0x71]	28480	1			T2	60		T8	10		T10	3
valid_sources[0x72]	27690	1			T2	37		T8	4		T11	1
valid_sources[0x73]	30795	1			T2	42		T8	1		T10	3
valid_sources[0x74]	41803	1			T2	31		T3	2		T8	3
valid_sources[0x75]	30891	1			T2	41		T8	3		T10	12
valid_sources[0x76]	31648	1			T2	34		T8	5		T39	1
valid_sources[0x77]	32847	1			T2	54		T8	6		T10	6
valid_sources[0x78]	29030	1			T2	53		T10	16		T11	1
valid_sources[0x79]	31607	1			T2	42		T3	2		T8	7
valid_sources[0x7a]	29612	1			T2	38		T8	2		T10	4
valid_sources[0x7b]	28907	1			T2	39		T8	6		T10	1
valid_sources[0x7c]	29248	1			T2	37		T3	1		T8	3
valid_sources[0x7d]	30971	1			T2	39		T8	2		T41	1
valid_sources[0x7e]	32757	1			T2	36		T3	2		T8	1
valid_sources[0x7f]	30019	1			T2	24		T8	7		T41	1
valid_sources[0x80]	29775	1			T2	41		T8	3		T39	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1194231

1

T1

1

T2

535

T4

1

values[0x0]

all_enables

biggest_size

1661514

1

T2

1535

T4

1

T5

2

values[0x1]

all_enables

biggest_size

1637285

1

T2

1573

T5

6

T6

59