Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3932205

1

T2

6963

T3

81

T4

19

full_word

4492475

1

T1

1

T2

3643

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8424270	1			T1	1		T2	10606		T3	81
auto[TlIntgErrCmd]	137	1			T129	3		T130	8		T131	3
auto[TlIntgErrData]	139	1			T129	5		T130	10		T131	4
auto[TlIntgErrBoth]	134	1			T129	2		T130	12		T131	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4759432

1

T1

1

T2

6894

T3

81

auto[1]

3665248

1

T2

3712

T4

4

T5

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3564731	1			T2	6359		T3	81		T4	16
auto[TlIntgErrNone]	partial	auto[1]	367102	1			T2	604		T4	3		T5	2
auto[TlIntgErrNone]	full_word	auto[0]	1194503	1			T1	1		T2	535		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3297934	1			T2	3108		T4	1		T5	8
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T129	3		T130	2		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T130	5		T177	5		T205	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T177	1		T206	1		T207	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T130	1		T131	1		T202	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T129	1		T130	4		T131	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T129	4		T130	5		T131	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T130	1		T204	1		T206	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T177	1		T205	1		T203	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T129	1		T130	2		T177	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T129	1		T130	9		T131	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T130	1		T205	1		T203	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T208	3		T207	1		-	-