Unified Coverage Report :: Module :: prim_generic_clock_gating

Module : prim_generic_clock_gating

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_pt_sck_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_clock_gating

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T1 T2 T3 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T1 T2 T3 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_gating

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T15
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : prim_generic_clock_gating

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5