Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_mode_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_mode_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_mode_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_swap_en_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_swap_en_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_addr_swap_en_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_mbyte_en_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_mbyte_en_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_mbyte_en_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_size_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_size_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_size_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_en_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_en_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_dummy_en_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_en_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_en_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_en_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_dir_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_dir_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_dir_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_swap_en_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_swap_en_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_payload_swap_en_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_read_pipeline_mode_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_read_pipeline_mode_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_read_pipeline_mode_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_upload_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_upload_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_upload_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_busy_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_busy_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_busy_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_valid_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_valid_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_4_valid_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_opcode_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_opcode_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_opcode_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_mode_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_mode_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_mode_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_swap_en_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_swap_en_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_addr_swap_en_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_mbyte_en_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_mbyte_en_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_mbyte_en_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_size_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_size_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_size_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_en_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_en_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_dummy_en_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_en_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_en_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_en_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_dir_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_dir_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_dir_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_swap_en_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_swap_en_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_payload_swap_en_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_read_pipeline_mode_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_read_pipeline_mode_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_read_pipeline_mode_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_upload_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_upload_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_upload_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_busy_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_busy_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_busy_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_valid_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_valid_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_5_valid_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_opcode_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_opcode_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_opcode_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_addr_mode_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T2 T7 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T7 T8
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_addr_mode_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_6_addr_mode_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |