Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	2951332	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	2951332	0	0
T2	556398	832	0	0
T3	1335	0	0	0
T4	1313	0	0	0
T5	2646	0	0	0
T6	2127	100	0	0
T7	10581	832	0	0
T8	8729	832	0	0
T9	3476	832	0	0
T10	3742	1670	0	0
T15	0	832	0	0
T16	0	832	0	0
T26	937	0	0	0
T39	0	1671	0	0
T41	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	3194431	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	3194431	0	0
T2	556398	832	0	0
T3	1335	0	0	0
T4	1313	0	0	0
T5	2646	0	0	0
T6	2127	100	0	0
T7	10581	3760	0	0
T8	8729	832	0	0
T9	3476	832	0	0
T10	3742	839	0	0
T15	0	832	0	0
T16	0	832	0	0
T26	937	0	0	0
T39	0	841	0	0
T41	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	200197	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	200197	0	0
T2	556398	254	0	0
T3	1335	0	0	0
T4	1313	0	0	0
T5	2646	0	0	0
T6	2127	100	0	0
T7	10581	0	0	0
T8	8729	0	0	0
T9	3476	0	0	0
T10	3742	0	0	0
T14	0	123	0	0
T20	0	4	0	0
T26	937	0	0	0
T29	0	658	0	0
T31	0	44	0	0
T32	0	19	0	0
T41	0	100	0	0
T45	0	100	0	0
T46	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	448354	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	448354	0	0
T2	556398	254	0	0
T3	1335	0	0	0
T4	1313	0	0	0
T5	2646	0	0	0
T6	2127	100	0	0
T7	10581	0	0	0
T8	8729	0	0	0
T9	3476	0	0	0
T10	3742	0	0	0
T14	0	123	0	0
T20	0	17	0	0
T26	937	0	0	0
T29	0	658	0	0
T31	0	44	0	0
T32	0	19	0	0
T41	0	100	0	0
T45	0	453	0	0
T46	0	441	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	6736595	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	6736595	0	0
T1	865	1	0	0
T2	556398	9552	0	0
T3	1335	81	0	0
T4	1313	21	0	0
T5	2646	11	0	0
T6	2127	1	0	0
T7	10581	43	0	0
T8	8729	118	0	0
T9	3476	108	0	0
T10	3742	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471287735	13448439	0	0
DepthKnown_A	471287735	471152861	0	0
RvalidKnown_A	471287735	471152861	0	0
WreadyKnown_A	471287735	471152861	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	13448439	0	0
T1	865	1	0	0
T2	556398	9520	0	0
T3	1335	81	0	0
T4	1313	21	0	0
T5	2646	11	0	0
T6	2127	1	0	0
T7	10581	195	0	0
T8	8729	118	0	0
T9	3476	108	0	0
T10	3742	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471287735	471152861	0	0
T1	865	793	0	0
T2	556398	556338	0	0
T3	1335	1257	0	0
T4	1313	1219	0	0
T5	2646	2583	0	0
T6	2127	2069	0	0
T7	10581	10496	0	0
T8	8729	8637	0	0
T9	3476	3401	0	0
T10	3742	3692	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0