Module Definition
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Module Instance : tb.dut.u_readcmd.u_readsram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.77 98.25 100.00 100.00 90.62 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.10 97.79 86.54 100.00 91.18 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 96.32 100.00 80.00 84.62 100.00 u_readcmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_fifo 97.62 100.00 90.48 100.00 100.00
u_sram_fifo 88.63 95.00 76.19 83.33 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spid_readsram
Line No.TotalCoveredPercent
TOTAL575698.25
CONT_ASSIGN11811100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
ALWAYS16644100.00
ALWAYS17266100.00
ALWAYS17955100.00
CONT_ASSIGN18911100.00
ALWAYS19555100.00
ALWAYS22533100.00
ALWAYS230262596.15
CONT_ASSIGN34611100.00

117 logic strb_set; 118 1/1 assign strb_set = addr_latched_i; Tests: T1 T2 T3  119 120 logic [31:0] next_address; 121 122 logic sram_req; 123 1/1 assign sram_l2m_o.req = sram_req; Tests: T1 T2 T3  124 assign sram_l2m_o.we = 1'b 0; 125 assign sram_l2m_o.wdata = '0; 126 assign sram_l2m_o.wstrb = SramStrbW'(0); // no write 127 128 sram_addr_t sram_addr; 129 1/1 assign sram_l2m_o.addr = sram_addr; Tests: T1 T2 T3  130 131 sram_data_t sram_data; 132 133 // FIFO 134 logic fifo_wvalid, fifo_wready; 135 spi_byte_t fifo_wdata; 136 137 logic sram_d_valid, sram_d_ready; 138 logic sram_fifo_full; 139 logic unused_sram_depth; 140 141 // Unused 142 logic unused_fifo_full; 143 logic [1:0] unused_fifo_depth; 144 145 logic unused_next_address; 146 1/1 assign unused_next_address = ^{next_address[31:$bits(sram_addr_t)+1],next_address[1:0]}; Tests: T1 T2 T3  147 148 ////////////// 149 // Datapath // 150 ////////////// 151 152 // Mailbox hit detection 153 // mailbox_hit_i only checks current_address_i. 154 // SRAM logic sends request to the next address based on the condition. 155 // Need to check the mailbox hit based on the SRAM address rather than 156 // current_address. 157 localparam logic [31:0] MailboxMask = {{30-MailboxAw{1'b1}}, {2+MailboxAw{1'b0}}}; 158 159 logic [31:0] mailbox_masked_addr; 160 1/1 assign mailbox_masked_addr = (next_address & MailboxMask); Tests: T1 T2 T3  161 1/1 assign mailbox_hit = mailbox_en_i Tests: T1 T2 T3  162 && (mailbox_masked_addr == mailbox_addr_i); 163 164 logic sram_latched; // sram request sent 165 always_ff @(posedge clk_i or negedge rst_ni) begin 166 2/2 if (!rst_ni) sram_latched <= 1'b 0; Tests: T1 T2 T3  | T1 T2 T3  167 2/2 else if (sram_req) sram_latched <= 1'b 1; Tests: T2 T8 T9  | T2 T16 T18  MISSING_ELSE 168 end 169 170 logic [1:0] strb; 171 always_ff @(posedge clk_i or negedge rst_ni) begin 172 2/2 if (!rst_ni) strb <= 2'b 00; Tests: T1 T2 T3  | T1 T2 T3  173 2/2 else if (data_inc) strb <= strb + 1'b 1; // Overflow is OK Tests: T2 T8 T9  | T2 T16 T18  174 2/2 else if (strb_set) strb <= current_address_i[1:0]; Tests: T2 T8 T9  | T2 T8 T9  MISSING_ELSE 175 end 176 177 // fifo_wdata 178 always_comb begin 179 1/1 unique case (strb) Tests: T1 T2 T3  180 1/1 2'b 00: fifo_wdata = sram_data[ 7: 0]; Tests: T1 T2 T3  181 1/1 2'b 01: fifo_wdata = sram_data[15: 8]; Tests: T2 T16 T18  182 1/1 2'b 10: fifo_wdata = sram_data[23:16]; Tests: T2 T16 T18  183 1/1 2'b 11: fifo_wdata = sram_data[31:24]; Tests: T2 T16 T18  184 default: fifo_wdata = '0; 185 endcase 186 end 187 188 // Address calculation 189 1/1 assign next_address = (addr_sel == AddrContinuous) Tests: T1 T2 T3  190 ? {current_address_i[31:2] + 1'b1, 2'b00} 191 : current_address_i; 192 193 // Sram Address 194 always_comb begin 195 1/1 if (sfdp_hit_i) begin Tests: T1 T2 T3  196 1/1 sram_addr = SfdpBaseAddr | sram_addr_t'(next_address[2+:SfdpAw]); Tests: T2 T52 T53  197 1/1 end else if (mailbox_hit) begin Tests: T1 T2 T3  198 1/1 sram_addr = MailboxBaseAddr | sram_addr_t'(next_address[2+:MailboxAw]); Tests: T2 T56 T57  199 end else begin 200 1/1 sram_addr = ReadBaseAddr | sram_addr_t'(next_address[2+:ReadBufAw]); Tests: T1 T2 T3  201 end 202 end 203 204 /////////////////// 205 // State Machine // 206 /////////////////// 207 208 /* 209 _ _ _ _ _ 210 SCK | |_| |_| |_| |_| |_| 211 ___ ___ ___ ___ 212 ADDR X___X___X___X___X 213 3 2 1 0 214 ___ 215 S.RE / \__________ 216 ___ 217 S.R.V _____/ \______ 218 219 STRB / V \ 220 221 State Idle X P X Push 222 */ 223 224 always_ff @(posedge clk_i or negedge rst_ni) begin 225 2/2 if (!rst_ni) st_q <= StIdle; Tests: T1 T2 T3  | T1 T2 T3  226 1/1 else st_q <= st_d; Tests: T2 T8 T9  227 end 228 229 always_comb begin 230 1/1 st_d = st_q; Tests: T1 T2 T3  231 232 1/1 fifo_wvalid = 1'b 0; Tests: T1 T2 T3  233 234 1/1 addr_sel = AddrInput; Tests: T1 T2 T3  235 1/1 data_inc = 1'b 0; Tests: T1 T2 T3  236 237 1/1 sram_req = 1'b 0; Tests: T1 T2 T3  238 1/1 sram_d_ready = 1'b 0; Tests: T1 T2 T3  239 240 1/1 unique case (st_q) Tests: T1 T2 T3  241 StIdle: begin 242 1/1 addr_sel = AddrInput; Tests: T1 T2 T3  243 244 1/1 if (sram_read_req_i) begin Tests: T1 T2 T3  245 1/1 sram_req = 1'b 1; Tests: T2 T16 T18  246 end MISSING_ELSE 247 248 1/1 if ((sram_read_req_i || sram_latched) && strb_set) begin Tests: T1 T2 T3  249 // Regardless of permitted or not, FSM moves to StPush. 250 // If not permitted, FSM will psh garbage data to the FIFO 251 1/1 st_d = StPush; Tests: T2 T16 T18  252 end else begin 253 1/1 st_d = StIdle; Tests: T1 T2 T3  254 end 255 end 256 257 StPush: begin 258 1/1 if (sram_d_valid) begin Tests: T2 T16 T18  259 1/1 fifo_wvalid = 1'b 1; // push to FIFO Tests: T2 T16 T18  260 end MISSING_ELSE 261 262 2/2 if (fifo_wready) data_inc = 1'b 1; Tests: T2 T16 T18  | T2 T16 T18  MISSING_ELSE 263 264 1/1 if (strb == 2'b 11 && fifo_wready) begin Tests: T2 T16 T18  265 // pushed all bytes to FIFO 266 1/1 st_d = StActive; Tests: T2 T16 T18  267 268 1/1 sram_d_ready = 1'b 1; Tests: T2 T16 T18  269 end else begin 270 1/1 st_d = StPush; Tests: T2 T16 T18  271 end 272 end 273 274 StActive: begin 275 // Assume the SRAM logic is faster than update of current_address_i. 276 // ICEBOX(#18352): Put assertion. 277 1/1 addr_sel = AddrContinuous; // Pointing to next_address to check mailbox hit Tests: T2 T16 T18  278 1/1 if (!sram_fifo_full) begin Tests: T2 T16 T18  279 1/1 st_d = StPush; Tests: T2 T16 T18  280 281 1/1 sram_req = 1'b 1; Tests: T2 T16 T18  282 end else begin 283 0/1 ==> st_d = StActive; 284 end 285 end 286 287 default: begin 288 st_d = StIdle; 289 end 290 endcase 291 end 292 293 ////////////// 294 // Instance // 295 ////////////// 296 prim_fifo_sync #( 297 .Width ($bits(sram_data_t)), 298 .Pass (1'b 1), 299 .Depth (1), 300 .OutputZeroIfEmpty (1'b 0) 301 ) u_sram_fifo ( 302 .clk_i, 303 .rst_ni, 304 305 .clr_i (1'b 0), 306 307 .wvalid_i (sram_m2l_i.rvalid), 308 .wready_o (), 309 .wdata_i (sram_m2l_i.rdata), 310 311 .rvalid_o (sram_d_valid), 312 .rready_i (sram_d_ready), 313 .rdata_o (sram_data), 314 315 .full_o (sram_fifo_full), 316 .depth_o (unused_sram_depth), 317 .err_o () 318 ); 319 320 prim_fifo_sync #( 321 .Width ($bits(spi_byte_t)), 322 .Pass (1'b1), 323 .Depth (2), 324 .OutputZeroIfEmpty (1'b0) 325 ) u_fifo ( 326 .clk_i, 327 .rst_ni, 328 329 .clr_i (1'b 0), 330 331 .wvalid_i (fifo_wvalid), 332 .wready_o (fifo_wready), // always assume empty space 333 .wdata_i (fifo_wdata ), 334 335 .rvalid_o (fifo_rvalid_o), 336 .rready_i (fifo_rready_i), 337 .rdata_o (fifo_rdata_o ), 338 339 .full_o (unused_fifo_full ), 340 .depth_o (unused_fifo_depth), 341 .err_o () 342 ); 343 344 // ICEBOX(#18353): Handle SRAM integrity errors 345 sram_err_t unused_sram_rerror; 346 1/1 assign unused_sram_rerror = sram_m2l_i.rerror; Tests: T1 T2 T3 

Cond Coverage for Module : spid_readsram
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       161
 EXPRESSION (mailbox_en_i && (mailbox_masked_addr == mailbox_addr_i))
             ------1-----    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T9
11CoveredT2,T56,T57

 LINE       161
 SUB-EXPRESSION (mailbox_masked_addr == mailbox_addr_i)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION ((addr_sel == AddrContinuous) ? ({(current_address_i[31:2] + 1'b1), 2'b0}) : current_address_i)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T18

 LINE       189
 SUB-EXPRESSION (addr_sel == AddrContinuous)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T18

 LINE       248
 EXPRESSION ((sram_read_req_i || sram_latched) && strb_set)
             ----------------1----------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T18
11CoveredT2,T16,T18

 LINE       248
 SUB-EXPRESSION (sram_read_req_i || sram_latched)
                 -------1-------    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T16,T18
10CoveredT2,T16,T18

 LINE       264
 EXPRESSION ((strb == 2'b11) && fifo_wready)
             -------1-------    -----2-----
-1--2-StatusTests
01CoveredT2,T16,T18
10CoveredT2,T16,T18
11CoveredT2,T16,T18

 LINE       264
 SUB-EXPRESSION (strb == 2'b11)
                -------1-------
-1-StatusTests
0CoveredT2,T16,T18
1CoveredT2,T16,T18

FSM Coverage for Module : spid_readsram
Summary for FSM :: st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 3 3 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StActive 266 Covered T2,T16,T18
StIdle 253 Covered T1,T2,T3
StPush 251 Covered T2,T16,T18


transitionsLine No.CoveredTests
StActive->StPush 279 Covered T2,T16,T18
StIdle->StPush 251 Covered T2,T16,T18
StPush->StActive 266 Covered T2,T16,T18



Branch Coverage for Module : spid_readsram
Line No.TotalCoveredPercent
Branches 32 29 90.62
TERNARY 189 2 2 100.00
IF 166 3 3 100.00
IF 172 4 4 100.00
CASE 179 5 4 80.00
IF 195 3 3 100.00
IF 225 2 2 100.00
CASE 240 13 11 84.62


189 assign next_address = (addr_sel == AddrContinuous) 190 ? {current_address_i[31:2] + 1'b1, 2'b00} -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T16,T18
0 Covered T1,T2,T3


166 if (!rst_ni) sram_latched <= 1'b 0; -1- ==> 167 else if (sram_req) sram_latched <= 1'b 1; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T16,T18
0 0 Covered T2,T8,T9


172 if (!rst_ni) strb <= 2'b 00; -1- ==> 173 else if (data_inc) strb <= strb + 1'b 1; // Overflow is OK -2- ==> 174 else if (strb_set) strb <= current_address_i[1:0]; -3- ==> MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T16,T18
0 0 1 Covered T2,T8,T9
0 0 0 Covered T2,T8,T9


179 unique case (strb) -1- 180 2'b 00: fifo_wdata = sram_data[ 7: 0]; ==> 181 2'b 01: fifo_wdata = sram_data[15: 8]; ==> 182 2'b 10: fifo_wdata = sram_data[23:16]; ==> 183 2'b 11: fifo_wdata = sram_data[31:24]; ==> 184 default: fifo_wdata = '0; ==>

Branches:
-1-StatusTests
2'b00 Covered T1,T2,T3
2'b01 Covered T2,T16,T18
2'b10 Covered T2,T16,T18
2'b11 Covered T2,T16,T18
default Not Covered


195 if (sfdp_hit_i) begin -1- 196 sram_addr = SfdpBaseAddr | sram_addr_t'(next_address[2+:SfdpAw]); ==> 197 end else if (mailbox_hit) begin -2- 198 sram_addr = MailboxBaseAddr | sram_addr_t'(next_address[2+:MailboxAw]); ==> 199 end else begin 200 sram_addr = ReadBaseAddr | sram_addr_t'(next_address[2+:ReadBufAw]); ==>

Branches:
-1--2-StatusTests
1 - Covered T2,T52,T53
0 1 Covered T2,T56,T57
0 0 Covered T1,T2,T3


225 if (!rst_ni) st_q <= StIdle; -1- ==> 226 else st_q <= st_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T8,T9


240 unique case (st_q) -1- 241 StIdle: begin 242 addr_sel = AddrInput; 243 244 if (sram_read_req_i) begin -2- 245 sram_req = 1'b 1; ==> 246 end MISSING_ELSE ==> 247 248 if ((sram_read_req_i || sram_latched) && strb_set) begin -3- 249 // Regardless of permitted or not, FSM moves to StPush. 250 // If not permitted, FSM will psh garbage data to the FIFO 251 st_d = StPush; ==> 252 end else begin 253 st_d = StIdle; ==> 254 end 255 end 256 257 StPush: begin 258 if (sram_d_valid) begin -4- 259 fifo_wvalid = 1'b 1; // push to FIFO ==> 260 end MISSING_ELSE ==> 261 262 if (fifo_wready) data_inc = 1'b 1; -5- ==> MISSING_ELSE ==> 263 264 if (strb == 2'b 11 && fifo_wready) begin -6- 265 // pushed all bytes to FIFO 266 st_d = StActive; ==> 267 268 sram_d_ready = 1'b 1; 269 end else begin 270 st_d = StPush; ==> 271 end 272 end 273 274 StActive: begin 275 // Assume the SRAM logic is faster than update of current_address_i. 276 // ICEBOX(#18352): Put assertion. 277 addr_sel = AddrContinuous; // Pointing to next_address to check mailbox hit 278 if (!sram_fifo_full) begin -7- 279 st_d = StPush; ==> 280 281 sram_req = 1'b 1; 282 end else begin 283 st_d = StActive; ==> 284 end 285 end 286 287 default: begin 288 st_d = StIdle; ==>

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle 1 - - - - - Covered T2,T16,T18
StIdle 0 - - - - - Covered T1,T2,T3
StIdle - 1 - - - - Covered T2,T16,T18
StIdle - 0 - - - - Covered T1,T2,T3
StPush - - 1 - - - Covered T2,T16,T18
StPush - - 0 - - - Covered T21,T52,T81
StPush - - - 1 - - Covered T2,T16,T18
StPush - - - 0 - - Covered T2,T16,T18
StPush - - - - 1 - Covered T2,T16,T18
StPush - - - - 0 - Covered T2,T16,T18
StActive - - - - - 1 Covered T2,T16,T18
StActive - - - - - 0 Not Covered
default - - - - - - Not Covered


Assert Coverage for Module : spid_readsram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrLatchedPulse_M 148386066 70793 0 0
FifoNotEmpty_A 148386066 4109397 0 0
NotOverflow_A 148386066 1036760 0 0
ReqStrbRelation_M 148386066 7526 0 0
SramDataReturnRequirement_M 148386066 1036289 0 0
SramReadOnly_A 148386066 1036760 0 0


AddrLatchedPulse_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 70793 0 0
T2 81023 32 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 12 0 0
T9 80 2 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 4 0 0
T16 116248 22 0 0
T17 105809 0 0 0
T18 0 30 0 0
T20 0 54 0 0
T21 0 16 0 0
T22 0 16 0 0
T23 0 2 0 0

FifoNotEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 4109397 0 0
T2 81023 769 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 0 0 0
T9 80 0 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 0 0 0
T16 116248 5394 0 0
T17 105809 0 0 0
T18 0 2146 0 0
T21 0 3622 0 0
T22 0 3600 0 0
T47 0 3221 0 0
T51 0 5446 0 0
T56 0 11376 0 0
T57 0 2342 0 0
T58 0 512 0 0

NotOverflow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 1036760 0 0
T2 81023 196 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 0 0 0
T9 80 0 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 0 0 0
T16 116248 1352 0 0
T17 105809 0 0 0
T18 0 546 0 0
T21 0 917 0 0
T22 0 909 0 0
T47 0 816 0 0
T51 0 1374 0 0
T56 0 2848 0 0
T57 0 594 0 0
T58 0 130 0 0

ReqStrbRelation_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 7526 0 0
T2 81023 3 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 0 0 0
T9 80 0 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 0 0 0
T16 116248 4 0 0
T17 105809 0 0 0
T18 0 8 0 0
T21 0 8 0 0
T22 0 8 0 0
T47 0 8 0 0
T51 0 10 0 0
T56 0 4 0 0
T57 0 8 0 0
T58 0 2 0 0

SramDataReturnRequirement_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 1036289 0 0
T2 81023 196 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 0 0 0
T9 80 0 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 0 0 0
T16 116248 1352 0 0
T17 105809 0 0 0
T18 0 546 0 0
T21 0 916 0 0
T22 0 909 0 0
T47 0 816 0 0
T51 0 1374 0 0
T56 0 2848 0 0
T57 0 594 0 0
T58 0 130 0 0

SramReadOnly_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148386066 1036760 0 0
T2 81023 196 0 0
T4 72 0 0 0
T5 216 0 0 0
T8 96 0 0 0
T9 80 0 0 0
T12 829 0 0 0
T14 24001 0 0 0
T15 32 0 0 0
T16 116248 1352 0 0
T17 105809 0 0 0
T18 0 546 0 0
T21 0 917 0 0
T22 0 909 0 0
T47 0 816 0 0
T51 0 1374 0 0
T56 0 2848 0 0
T57 0 594 0 0
T58 0 130 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%