Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3538 |
0 |
0 |
T125 |
6964 |
248 |
0 |
0 |
T126 |
5341 |
72 |
0 |
0 |
T127 |
5195 |
12 |
0 |
0 |
T128 |
7123 |
235 |
0 |
0 |
T130 |
98806 |
9 |
0 |
0 |
T132 |
13035 |
7 |
0 |
0 |
T135 |
19782 |
266 |
0 |
0 |
T143 |
5232 |
14 |
0 |
0 |
T145 |
6268 |
2 |
0 |
0 |
T177 |
81519 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3513 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
119 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
3 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
522 |
0 |
0 |
T178 |
78891 |
114 |
0 |
0 |
T179 |
5413 |
9 |
0 |
0 |
T180 |
19310 |
62 |
0 |
0 |
T181 |
20115 |
114 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3590 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
107 |
0 |
0 |
T145 |
6268 |
6 |
0 |
0 |
T147 |
7280 |
10 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
504 |
0 |
0 |
T178 |
78891 |
129 |
0 |
0 |
T179 |
5413 |
8 |
0 |
0 |
T180 |
19310 |
86 |
0 |
0 |
T181 |
20115 |
111 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
4150 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
246 |
0 |
0 |
T145 |
6268 |
16 |
0 |
0 |
T147 |
7280 |
9 |
0 |
0 |
T149 |
7205 |
15 |
0 |
0 |
T154 |
79972 |
555 |
0 |
0 |
T178 |
78891 |
98 |
0 |
0 |
T179 |
5413 |
11 |
0 |
0 |
T180 |
19310 |
53 |
0 |
0 |
T181 |
20115 |
53 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13514 |
0 |
0 |
T115 |
3182 |
2 |
0 |
0 |
T130 |
98806 |
1776 |
0 |
0 |
T145 |
6268 |
124 |
0 |
0 |
T147 |
7280 |
114 |
0 |
0 |
T149 |
7205 |
126 |
0 |
0 |
T154 |
79972 |
467 |
0 |
0 |
T178 |
78891 |
169 |
0 |
0 |
T179 |
5413 |
2 |
0 |
0 |
T180 |
19310 |
61 |
0 |
0 |
T181 |
20115 |
65 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13643 |
0 |
0 |
T115 |
3182 |
6 |
0 |
0 |
T130 |
98806 |
2009 |
0 |
0 |
T137 |
24713 |
1 |
0 |
0 |
T145 |
6268 |
114 |
0 |
0 |
T147 |
7280 |
102 |
0 |
0 |
T149 |
7205 |
111 |
0 |
0 |
T154 |
79972 |
542 |
0 |
0 |
T178 |
78891 |
163 |
0 |
0 |
T179 |
5413 |
6 |
0 |
0 |
T180 |
19310 |
47 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13000 |
0 |
0 |
T115 |
3182 |
1 |
0 |
0 |
T130 |
98806 |
1641 |
0 |
0 |
T145 |
6268 |
130 |
0 |
0 |
T147 |
7280 |
155 |
0 |
0 |
T149 |
7205 |
231 |
0 |
0 |
T154 |
79972 |
500 |
0 |
0 |
T178 |
78891 |
136 |
0 |
0 |
T180 |
19310 |
81 |
0 |
0 |
T181 |
20115 |
49 |
0 |
0 |
T182 |
77035 |
557 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13789 |
0 |
0 |
T115 |
3182 |
1 |
0 |
0 |
T130 |
98806 |
1759 |
0 |
0 |
T145 |
6268 |
9 |
0 |
0 |
T147 |
7280 |
132 |
0 |
0 |
T149 |
7205 |
8 |
0 |
0 |
T154 |
79972 |
465 |
0 |
0 |
T178 |
78891 |
131 |
0 |
0 |
T179 |
5413 |
156 |
0 |
0 |
T180 |
19310 |
106 |
0 |
0 |
T181 |
20115 |
88 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
12747 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
2020 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
8 |
0 |
0 |
T149 |
7205 |
109 |
0 |
0 |
T154 |
79972 |
468 |
0 |
0 |
T178 |
78891 |
117 |
0 |
0 |
T179 |
5413 |
141 |
0 |
0 |
T180 |
19310 |
39 |
0 |
0 |
T181 |
20115 |
73 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13902 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
1756 |
0 |
0 |
T145 |
6268 |
101 |
0 |
0 |
T147 |
7280 |
226 |
0 |
0 |
T149 |
7205 |
242 |
0 |
0 |
T154 |
79972 |
540 |
0 |
0 |
T178 |
78891 |
121 |
0 |
0 |
T179 |
5413 |
6 |
0 |
0 |
T180 |
19310 |
50 |
0 |
0 |
T181 |
20115 |
20 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
13888 |
0 |
0 |
T115 |
3182 |
8 |
0 |
0 |
T130 |
98806 |
1686 |
0 |
0 |
T145 |
6268 |
7 |
0 |
0 |
T147 |
7280 |
133 |
0 |
0 |
T149 |
7205 |
198 |
0 |
0 |
T154 |
79972 |
534 |
0 |
0 |
T178 |
78891 |
173 |
0 |
0 |
T179 |
5413 |
126 |
0 |
0 |
T180 |
19310 |
64 |
0 |
0 |
T181 |
20115 |
62 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
14086 |
0 |
0 |
T130 |
98806 |
1356 |
0 |
0 |
T145 |
6268 |
6 |
0 |
0 |
T147 |
7280 |
143 |
0 |
0 |
T149 |
7205 |
10 |
0 |
0 |
T154 |
79972 |
452 |
0 |
0 |
T178 |
78891 |
119 |
0 |
0 |
T179 |
5413 |
129 |
0 |
0 |
T180 |
19310 |
36 |
0 |
0 |
T181 |
20115 |
113 |
0 |
0 |
T182 |
77035 |
511 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7677 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
859 |
0 |
0 |
T145 |
6268 |
45 |
0 |
0 |
T147 |
7280 |
49 |
0 |
0 |
T149 |
7205 |
39 |
0 |
0 |
T154 |
79972 |
484 |
0 |
0 |
T178 |
78891 |
118 |
0 |
0 |
T179 |
5413 |
75 |
0 |
0 |
T180 |
19310 |
110 |
0 |
0 |
T181 |
20115 |
85 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7571 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
867 |
0 |
0 |
T137 |
24713 |
2 |
0 |
0 |
T145 |
6268 |
66 |
0 |
0 |
T147 |
7280 |
50 |
0 |
0 |
T149 |
7205 |
101 |
0 |
0 |
T154 |
79972 |
450 |
0 |
0 |
T178 |
78891 |
157 |
0 |
0 |
T179 |
5413 |
46 |
0 |
0 |
T180 |
19310 |
115 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7674 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
825 |
0 |
0 |
T145 |
6268 |
54 |
0 |
0 |
T147 |
7280 |
47 |
0 |
0 |
T149 |
7205 |
57 |
0 |
0 |
T154 |
79972 |
491 |
0 |
0 |
T178 |
78891 |
132 |
0 |
0 |
T179 |
5413 |
71 |
0 |
0 |
T180 |
19310 |
61 |
0 |
0 |
T181 |
20115 |
59 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7402 |
0 |
0 |
T115 |
3182 |
9 |
0 |
0 |
T130 |
98806 |
686 |
0 |
0 |
T145 |
6268 |
62 |
0 |
0 |
T147 |
7280 |
10 |
0 |
0 |
T149 |
7205 |
35 |
0 |
0 |
T154 |
79972 |
471 |
0 |
0 |
T178 |
78891 |
155 |
0 |
0 |
T179 |
5413 |
63 |
0 |
0 |
T180 |
19310 |
118 |
0 |
0 |
T181 |
20115 |
97 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
6910 |
0 |
0 |
T115 |
3182 |
9 |
0 |
0 |
T130 |
98806 |
765 |
0 |
0 |
T145 |
6268 |
66 |
0 |
0 |
T147 |
7280 |
6 |
0 |
0 |
T149 |
7205 |
10 |
0 |
0 |
T154 |
79972 |
467 |
0 |
0 |
T178 |
78891 |
106 |
0 |
0 |
T179 |
5413 |
59 |
0 |
0 |
T180 |
19310 |
54 |
0 |
0 |
T181 |
20115 |
42 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
8398 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
920 |
0 |
0 |
T145 |
6268 |
35 |
0 |
0 |
T147 |
7280 |
69 |
0 |
0 |
T149 |
7205 |
54 |
0 |
0 |
T154 |
79972 |
488 |
0 |
0 |
T178 |
78891 |
140 |
0 |
0 |
T179 |
5413 |
57 |
0 |
0 |
T180 |
19310 |
67 |
0 |
0 |
T181 |
20115 |
60 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7905 |
0 |
0 |
T115 |
3182 |
1 |
0 |
0 |
T130 |
98806 |
741 |
0 |
0 |
T145 |
6268 |
39 |
0 |
0 |
T147 |
7280 |
2 |
0 |
0 |
T149 |
7205 |
122 |
0 |
0 |
T154 |
79972 |
471 |
0 |
0 |
T178 |
78891 |
98 |
0 |
0 |
T179 |
5413 |
9 |
0 |
0 |
T180 |
19310 |
54 |
0 |
0 |
T181 |
20115 |
82 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7973 |
0 |
0 |
T115 |
3182 |
11 |
0 |
0 |
T130 |
98806 |
752 |
0 |
0 |
T145 |
6268 |
5 |
0 |
0 |
T147 |
7280 |
56 |
0 |
0 |
T149 |
7205 |
64 |
0 |
0 |
T154 |
79972 |
423 |
0 |
0 |
T178 |
78891 |
165 |
0 |
0 |
T179 |
5413 |
50 |
0 |
0 |
T180 |
19310 |
122 |
0 |
0 |
T181 |
20115 |
39 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7565 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
975 |
0 |
0 |
T145 |
6268 |
81 |
0 |
0 |
T147 |
7280 |
54 |
0 |
0 |
T149 |
7205 |
64 |
0 |
0 |
T154 |
79972 |
467 |
0 |
0 |
T178 |
78891 |
169 |
0 |
0 |
T179 |
5413 |
50 |
0 |
0 |
T180 |
19310 |
65 |
0 |
0 |
T181 |
20115 |
48 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7119 |
0 |
0 |
T115 |
3182 |
9 |
0 |
0 |
T130 |
98806 |
680 |
0 |
0 |
T145 |
6268 |
73 |
0 |
0 |
T147 |
7280 |
11 |
0 |
0 |
T149 |
7205 |
6 |
0 |
0 |
T154 |
79972 |
505 |
0 |
0 |
T178 |
78891 |
139 |
0 |
0 |
T179 |
5413 |
45 |
0 |
0 |
T180 |
19310 |
69 |
0 |
0 |
T181 |
20115 |
73 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
8546 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
914 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
99 |
0 |
0 |
T149 |
7205 |
71 |
0 |
0 |
T154 |
79972 |
558 |
0 |
0 |
T178 |
78891 |
130 |
0 |
0 |
T179 |
5413 |
35 |
0 |
0 |
T180 |
19310 |
94 |
0 |
0 |
T181 |
20115 |
37 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7791 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
862 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
45 |
0 |
0 |
T149 |
7205 |
75 |
0 |
0 |
T154 |
79972 |
497 |
0 |
0 |
T178 |
78891 |
121 |
0 |
0 |
T179 |
5413 |
40 |
0 |
0 |
T180 |
19310 |
24 |
0 |
0 |
T181 |
20115 |
57 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7678 |
0 |
0 |
T115 |
3182 |
18 |
0 |
0 |
T130 |
98806 |
993 |
0 |
0 |
T145 |
6268 |
40 |
0 |
0 |
T147 |
7280 |
93 |
0 |
0 |
T149 |
7205 |
3 |
0 |
0 |
T154 |
79972 |
475 |
0 |
0 |
T178 |
78891 |
113 |
0 |
0 |
T179 |
5413 |
48 |
0 |
0 |
T180 |
19310 |
20 |
0 |
0 |
T181 |
20115 |
56 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7484 |
0 |
0 |
T115 |
3182 |
5 |
0 |
0 |
T130 |
98806 |
865 |
0 |
0 |
T145 |
6268 |
3 |
0 |
0 |
T147 |
7280 |
68 |
0 |
0 |
T149 |
7205 |
4 |
0 |
0 |
T154 |
79972 |
470 |
0 |
0 |
T178 |
78891 |
172 |
0 |
0 |
T179 |
5413 |
56 |
0 |
0 |
T180 |
19310 |
82 |
0 |
0 |
T181 |
20115 |
104 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7733 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
855 |
0 |
0 |
T145 |
6268 |
58 |
0 |
0 |
T147 |
7280 |
55 |
0 |
0 |
T149 |
7205 |
11 |
0 |
0 |
T154 |
79972 |
531 |
0 |
0 |
T178 |
78891 |
103 |
0 |
0 |
T179 |
5413 |
51 |
0 |
0 |
T180 |
19310 |
67 |
0 |
0 |
T181 |
20115 |
46 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7362 |
0 |
0 |
T115 |
3182 |
15 |
0 |
0 |
T130 |
98806 |
1000 |
0 |
0 |
T135 |
19782 |
8 |
0 |
0 |
T145 |
6268 |
7 |
0 |
0 |
T147 |
7280 |
11 |
0 |
0 |
T149 |
7205 |
112 |
0 |
0 |
T154 |
79972 |
500 |
0 |
0 |
T178 |
78891 |
134 |
0 |
0 |
T179 |
5413 |
3 |
0 |
0 |
T180 |
19310 |
63 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7422 |
0 |
0 |
T115 |
3182 |
1 |
0 |
0 |
T130 |
98806 |
689 |
0 |
0 |
T145 |
6268 |
13 |
0 |
0 |
T147 |
7280 |
41 |
0 |
0 |
T149 |
7205 |
41 |
0 |
0 |
T154 |
79972 |
442 |
0 |
0 |
T178 |
78891 |
108 |
0 |
0 |
T179 |
5413 |
8 |
0 |
0 |
T180 |
19310 |
36 |
0 |
0 |
T181 |
20115 |
98 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
6960 |
0 |
0 |
T115 |
3182 |
5 |
0 |
0 |
T130 |
98806 |
686 |
0 |
0 |
T135 |
19782 |
2 |
0 |
0 |
T145 |
6268 |
7 |
0 |
0 |
T147 |
7280 |
8 |
0 |
0 |
T149 |
7205 |
9 |
0 |
0 |
T154 |
79972 |
502 |
0 |
0 |
T178 |
78891 |
144 |
0 |
0 |
T179 |
5413 |
2 |
0 |
0 |
T180 |
19310 |
55 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7621 |
0 |
0 |
T115 |
3182 |
6 |
0 |
0 |
T130 |
98806 |
817 |
0 |
0 |
T145 |
6268 |
41 |
0 |
0 |
T147 |
7280 |
54 |
0 |
0 |
T149 |
7205 |
44 |
0 |
0 |
T154 |
79972 |
441 |
0 |
0 |
T178 |
78891 |
168 |
0 |
0 |
T180 |
19310 |
80 |
0 |
0 |
T181 |
20115 |
39 |
0 |
0 |
T182 |
77035 |
541 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7462 |
0 |
0 |
T115 |
3182 |
6 |
0 |
0 |
T130 |
98806 |
818 |
0 |
0 |
T145 |
6268 |
9 |
0 |
0 |
T147 |
7280 |
81 |
0 |
0 |
T149 |
7205 |
52 |
0 |
0 |
T154 |
79972 |
523 |
0 |
0 |
T178 |
78891 |
131 |
0 |
0 |
T179 |
5413 |
7 |
0 |
0 |
T180 |
19310 |
72 |
0 |
0 |
T181 |
20115 |
79 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7862 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
848 |
0 |
0 |
T137 |
24713 |
4 |
0 |
0 |
T145 |
6268 |
11 |
0 |
0 |
T147 |
7280 |
50 |
0 |
0 |
T149 |
7205 |
107 |
0 |
0 |
T154 |
79972 |
454 |
0 |
0 |
T178 |
78891 |
144 |
0 |
0 |
T179 |
5413 |
33 |
0 |
0 |
T180 |
19310 |
71 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
6856 |
0 |
0 |
T115 |
3182 |
12 |
0 |
0 |
T130 |
98806 |
636 |
0 |
0 |
T137 |
24713 |
1 |
0 |
0 |
T145 |
6268 |
70 |
0 |
0 |
T147 |
7280 |
7 |
0 |
0 |
T149 |
7205 |
85 |
0 |
0 |
T154 |
79972 |
484 |
0 |
0 |
T178 |
78891 |
143 |
0 |
0 |
T179 |
5413 |
34 |
0 |
0 |
T180 |
19310 |
47 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7162 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
701 |
0 |
0 |
T145 |
6268 |
30 |
0 |
0 |
T147 |
7280 |
38 |
0 |
0 |
T149 |
7205 |
5 |
0 |
0 |
T154 |
79972 |
464 |
0 |
0 |
T178 |
78891 |
165 |
0 |
0 |
T179 |
5413 |
3 |
0 |
0 |
T180 |
19310 |
53 |
0 |
0 |
T181 |
20115 |
50 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
7078 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
978 |
0 |
0 |
T145 |
6268 |
47 |
0 |
0 |
T147 |
7280 |
49 |
0 |
0 |
T149 |
7205 |
27 |
0 |
0 |
T154 |
79972 |
557 |
0 |
0 |
T178 |
78891 |
160 |
0 |
0 |
T180 |
19310 |
55 |
0 |
0 |
T181 |
20115 |
47 |
0 |
0 |
T182 |
77035 |
556 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3853 |
0 |
0 |
T115 |
3182 |
16 |
0 |
0 |
T130 |
98806 |
149 |
0 |
0 |
T145 |
6268 |
20 |
0 |
0 |
T147 |
7280 |
15 |
0 |
0 |
T149 |
7205 |
3 |
0 |
0 |
T154 |
79972 |
588 |
0 |
0 |
T178 |
78891 |
114 |
0 |
0 |
T179 |
5413 |
5 |
0 |
0 |
T180 |
19310 |
29 |
0 |
0 |
T181 |
20115 |
65 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3902 |
0 |
0 |
T115 |
3182 |
2 |
0 |
0 |
T130 |
98806 |
169 |
0 |
0 |
T137 |
24713 |
14 |
0 |
0 |
T145 |
6268 |
5 |
0 |
0 |
T147 |
7280 |
6 |
0 |
0 |
T149 |
7205 |
11 |
0 |
0 |
T154 |
79972 |
512 |
0 |
0 |
T178 |
78891 |
138 |
0 |
0 |
T179 |
5413 |
2 |
0 |
0 |
T180 |
19310 |
84 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3784 |
0 |
0 |
T115 |
3182 |
14 |
0 |
0 |
T130 |
98806 |
179 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
10 |
0 |
0 |
T149 |
7205 |
6 |
0 |
0 |
T154 |
79972 |
556 |
0 |
0 |
T178 |
78891 |
120 |
0 |
0 |
T179 |
5413 |
10 |
0 |
0 |
T180 |
19310 |
19 |
0 |
0 |
T181 |
20115 |
103 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3754 |
0 |
0 |
T115 |
3182 |
10 |
0 |
0 |
T130 |
98806 |
143 |
0 |
0 |
T145 |
6268 |
10 |
0 |
0 |
T147 |
7280 |
4 |
0 |
0 |
T149 |
7205 |
19 |
0 |
0 |
T154 |
79972 |
490 |
0 |
0 |
T178 |
78891 |
100 |
0 |
0 |
T179 |
5413 |
8 |
0 |
0 |
T180 |
19310 |
85 |
0 |
0 |
T181 |
20115 |
64 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
4491 |
0 |
0 |
T115 |
3182 |
8 |
0 |
0 |
T130 |
98806 |
315 |
0 |
0 |
T145 |
6268 |
6 |
0 |
0 |
T147 |
7280 |
12 |
0 |
0 |
T149 |
7205 |
2 |
0 |
0 |
T154 |
79972 |
581 |
0 |
0 |
T178 |
78891 |
112 |
0 |
0 |
T179 |
5413 |
25 |
0 |
0 |
T180 |
19310 |
99 |
0 |
0 |
T181 |
20115 |
48 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
6428 |
0 |
0 |
T25 |
119688 |
74 |
0 |
0 |
T33 |
6005 |
0 |
0 |
0 |
T35 |
0 |
30 |
0 |
0 |
T36 |
0 |
37 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T55 |
203778 |
0 |
0 |
0 |
T61 |
9649 |
0 |
0 |
0 |
T62 |
202575 |
0 |
0 |
0 |
T64 |
120983 |
0 |
0 |
0 |
T70 |
0 |
84 |
0 |
0 |
T82 |
546028 |
0 |
0 |
0 |
T91 |
0 |
33 |
0 |
0 |
T108 |
1333 |
0 |
0 |
0 |
T183 |
0 |
46 |
0 |
0 |
T184 |
0 |
6 |
0 |
0 |
T185 |
0 |
62 |
0 |
0 |
T186 |
0 |
19 |
0 |
0 |
T187 |
4305 |
0 |
0 |
0 |
T188 |
1190 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
4025 |
0 |
0 |
T115 |
3182 |
2 |
0 |
0 |
T130 |
98806 |
163 |
0 |
0 |
T145 |
6268 |
15 |
0 |
0 |
T147 |
7280 |
5 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
501 |
0 |
0 |
T178 |
78891 |
142 |
0 |
0 |
T179 |
5413 |
5 |
0 |
0 |
T180 |
19310 |
70 |
0 |
0 |
T181 |
20115 |
128 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3881 |
0 |
0 |
T115 |
3182 |
15 |
0 |
0 |
T130 |
98806 |
160 |
0 |
0 |
T145 |
6268 |
17 |
0 |
0 |
T147 |
7280 |
12 |
0 |
0 |
T149 |
7205 |
2 |
0 |
0 |
T154 |
79972 |
527 |
0 |
0 |
T178 |
78891 |
145 |
0 |
0 |
T179 |
5413 |
9 |
0 |
0 |
T180 |
19310 |
24 |
0 |
0 |
T181 |
20115 |
75 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3432 |
0 |
0 |
T115 |
3182 |
15 |
0 |
0 |
T130 |
98806 |
120 |
0 |
0 |
T145 |
6268 |
1 |
0 |
0 |
T147 |
7280 |
1 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
493 |
0 |
0 |
T178 |
78891 |
150 |
0 |
0 |
T179 |
5413 |
2 |
0 |
0 |
T180 |
19310 |
59 |
0 |
0 |
T181 |
20115 |
63 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3352 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
100 |
0 |
0 |
T145 |
6268 |
1 |
0 |
0 |
T147 |
7280 |
8 |
0 |
0 |
T149 |
7205 |
12 |
0 |
0 |
T154 |
79972 |
484 |
0 |
0 |
T178 |
78891 |
148 |
0 |
0 |
T179 |
5413 |
8 |
0 |
0 |
T180 |
19310 |
80 |
0 |
0 |
T181 |
20115 |
31 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3577 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
103 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
9 |
0 |
0 |
T149 |
7205 |
6 |
0 |
0 |
T154 |
79972 |
547 |
0 |
0 |
T178 |
78891 |
111 |
0 |
0 |
T179 |
5413 |
1 |
0 |
0 |
T180 |
19310 |
83 |
0 |
0 |
T181 |
20115 |
127 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3620 |
0 |
0 |
T115 |
3182 |
5 |
0 |
0 |
T130 |
98806 |
137 |
0 |
0 |
T145 |
6268 |
1 |
0 |
0 |
T147 |
7280 |
8 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
537 |
0 |
0 |
T178 |
78891 |
128 |
0 |
0 |
T179 |
5413 |
7 |
0 |
0 |
T180 |
19310 |
47 |
0 |
0 |
T181 |
20115 |
69 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
4458 |
0 |
0 |
T115 |
3182 |
11 |
0 |
0 |
T130 |
98806 |
331 |
0 |
0 |
T145 |
6268 |
14 |
0 |
0 |
T147 |
7280 |
12 |
0 |
0 |
T149 |
7205 |
8 |
0 |
0 |
T154 |
79972 |
494 |
0 |
0 |
T178 |
78891 |
130 |
0 |
0 |
T179 |
5413 |
5 |
0 |
0 |
T180 |
19310 |
90 |
0 |
0 |
T181 |
20115 |
62 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3474 |
0 |
0 |
T115 |
3182 |
17 |
0 |
0 |
T130 |
98806 |
136 |
0 |
0 |
T145 |
6268 |
13 |
0 |
0 |
T147 |
7280 |
6 |
0 |
0 |
T149 |
7205 |
8 |
0 |
0 |
T154 |
79972 |
544 |
0 |
0 |
T178 |
78891 |
143 |
0 |
0 |
T179 |
5413 |
1 |
0 |
0 |
T180 |
19310 |
35 |
0 |
0 |
T181 |
20115 |
27 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
4583 |
0 |
0 |
T115 |
3182 |
8 |
0 |
0 |
T130 |
98806 |
339 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
42 |
0 |
0 |
T149 |
7205 |
8 |
0 |
0 |
T154 |
79972 |
535 |
0 |
0 |
T178 |
78891 |
169 |
0 |
0 |
T179 |
5413 |
18 |
0 |
0 |
T180 |
19310 |
74 |
0 |
0 |
T181 |
20115 |
59 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3673 |
0 |
0 |
T115 |
3182 |
7 |
0 |
0 |
T130 |
98806 |
184 |
0 |
0 |
T145 |
6268 |
10 |
0 |
0 |
T147 |
7280 |
19 |
0 |
0 |
T149 |
7205 |
12 |
0 |
0 |
T154 |
79972 |
493 |
0 |
0 |
T178 |
78891 |
148 |
0 |
0 |
T179 |
5413 |
3 |
0 |
0 |
T180 |
19310 |
68 |
0 |
0 |
T181 |
20115 |
26 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3332 |
0 |
0 |
T115 |
3182 |
6 |
0 |
0 |
T130 |
98806 |
100 |
0 |
0 |
T145 |
6268 |
7 |
0 |
0 |
T147 |
7280 |
5 |
0 |
0 |
T149 |
7205 |
7 |
0 |
0 |
T154 |
79972 |
489 |
0 |
0 |
T178 |
78891 |
166 |
0 |
0 |
T179 |
5413 |
1 |
0 |
0 |
T180 |
19310 |
41 |
0 |
0 |
T181 |
20115 |
37 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3638 |
0 |
0 |
T115 |
3182 |
13 |
0 |
0 |
T130 |
98806 |
68 |
0 |
0 |
T135 |
19782 |
2 |
0 |
0 |
T145 |
6268 |
8 |
0 |
0 |
T147 |
7280 |
12 |
0 |
0 |
T149 |
7205 |
11 |
0 |
0 |
T154 |
79972 |
478 |
0 |
0 |
T178 |
78891 |
162 |
0 |
0 |
T179 |
5413 |
4 |
0 |
0 |
T180 |
19310 |
90 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3481 |
0 |
0 |
T115 |
3182 |
3 |
0 |
0 |
T130 |
98806 |
106 |
0 |
0 |
T145 |
6268 |
1 |
0 |
0 |
T147 |
7280 |
3 |
0 |
0 |
T149 |
7205 |
9 |
0 |
0 |
T154 |
79972 |
453 |
0 |
0 |
T178 |
78891 |
127 |
0 |
0 |
T179 |
5413 |
2 |
0 |
0 |
T180 |
19310 |
77 |
0 |
0 |
T181 |
20115 |
86 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3391 |
0 |
0 |
T115 |
3182 |
3 |
0 |
0 |
T130 |
98806 |
107 |
0 |
0 |
T145 |
6268 |
14 |
0 |
0 |
T147 |
7280 |
6 |
0 |
0 |
T149 |
7205 |
3 |
0 |
0 |
T154 |
79972 |
496 |
0 |
0 |
T178 |
78891 |
144 |
0 |
0 |
T179 |
5413 |
6 |
0 |
0 |
T180 |
19310 |
51 |
0 |
0 |
T181 |
20115 |
96 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3601 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
96 |
0 |
0 |
T145 |
6268 |
4 |
0 |
0 |
T147 |
7280 |
2 |
0 |
0 |
T149 |
7205 |
13 |
0 |
0 |
T154 |
79972 |
500 |
0 |
0 |
T178 |
78891 |
172 |
0 |
0 |
T179 |
5413 |
4 |
0 |
0 |
T180 |
19310 |
77 |
0 |
0 |
T181 |
20115 |
69 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471287735 |
3271 |
0 |
0 |
T115 |
3182 |
4 |
0 |
0 |
T130 |
98806 |
101 |
0 |
0 |
T145 |
6268 |
12 |
0 |
0 |
T147 |
7280 |
11 |
0 |
0 |
T149 |
7205 |
9 |
0 |
0 |
T154 |
79972 |
565 |
0 |
0 |
T178 |
78891 |
135 |
0 |
0 |
T179 |
5413 |
4 |
0 |
0 |
T180 |
19310 |
24 |
0 |
0 |
T181 |
20115 |
34 |
0 |
0 |