Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2632494	1			T1	1		T2	1		T3	1
all_values[1]	2632494	1			T1	1		T2	1		T3	1
all_values[2]	2632494	1			T1	1		T2	1		T3	1
all_values[3]	2632494	1			T1	1		T2	1		T3	1
all_values[4]	2632494	1			T1	1		T2	1		T3	1
all_values[5]	2632494	1			T1	1		T2	1		T3	1
all_values[6]	2632494	1			T1	1		T2	1		T3	1
all_values[7]	2632494	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20557710

1

T1

8

T2

8

T3

8

auto[1]

502242

1

T24

106

T37

7707

T38

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21034991

1

T1

8

T2

8

T3

8

auto[1]

24961

1

T24

70

T37

169

T38

22

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2574702	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11351	1			T24	6		T38	2		T49	102
all_values[0]	auto[1]	auto[0]	45808	1			T24	7		T37	1837		T38	2
all_values[0]	auto[1]	auto[1]	633	1			T24	6		T37	87		T38	3
all_values[1]	auto[0]	auto[0]	2554875	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7530	1			T24	5		T38	3		T49	81
all_values[1]	auto[1]	auto[0]	69523	1			T24	12		T37	1872		T38	6
all_values[1]	auto[1]	auto[1]	566	1			T24	3		T37	51		T39	2
all_values[2]	auto[0]	auto[0]	2520750	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2569	1			T24	4		T37	3		T185	33
all_values[2]	auto[1]	auto[0]	108891	1			T24	10		T37	1918		T38	4
all_values[2]	auto[1]	auto[1]	284	1			T24	2		T37	4		T39	5
all_values[3]	auto[0]	auto[0]	2593444	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	209	1			T24	6		T37	2		T39	4
all_values[3]	auto[1]	auto[0]	38626	1			T24	9		T37	2		T38	2
all_values[3]	auto[1]	auto[1]	215	1			T24	4		T39	6		T96	4
all_values[4]	auto[0]	auto[0]	2525478	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	223	1			T24	5		T37	5		T38	2
all_values[4]	auto[1]	auto[0]	106598	1			T24	8		T37	2		T38	4
all_values[4]	auto[1]	auto[1]	195	1			T24	7		T37	3		T38	2
all_values[5]	auto[0]	auto[0]	2618895	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	192	1			T24	4		T37	5		T38	3
all_values[5]	auto[1]	auto[0]	13217	1			T24	7		T37	5		T38	3
all_values[5]	auto[1]	auto[1]	190	1			T24	5		T37	2		T96	4
all_values[6]	auto[0]	auto[0]	2625580	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	195	1			T24	3		T37	2		T38	3
all_values[6]	auto[1]	auto[0]	6494	1			T24	8		T38	3		T39	2
all_values[6]	auto[1]	auto[1]	225	1			T24	5		T37	3		T39	2
all_values[7]	auto[0]	auto[0]	2521542	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	175	1			T24	1		T37	1		T38	1
all_values[7]	auto[1]	auto[0]	110568	1			T24	9		T37	1920		T38	5
all_values[7]	auto[1]	auto[1]	209	1			T24	4		T37	1		T38	3