Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.68 58.68 91.87 91.87 78.15 78.15 62.60 62.60 8.89 8.89 88.35 88.35 70.14 70.14 10.74 10.74 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1725724314
73.03 14.36 94.67 2.81 85.65 7.49 65.06 2.46 60.00 51.11 91.90 3.55 77.57 7.43 36.39 25.64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3158429357
79.86 6.83 95.80 1.12 87.75 2.10 78.64 13.58 84.44 24.44 93.45 1.56 79.29 1.71 39.65 3.27 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2879311828
83.94 4.08 97.90 2.10 91.57 3.83 82.19 3.54 88.89 4.44 96.40 2.94 84.71 5.43 45.94 6.29 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1909982677
85.95 2.01 97.93 0.03 91.64 0.06 82.38 0.20 88.89 0.00 96.46 0.07 84.71 0.00 59.65 13.71 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1427533398
87.68 1.73 97.95 0.02 91.81 0.17 83.37 0.98 88.89 0.00 96.50 0.03 93.43 8.71 61.83 2.18 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.4017984013
89.15 1.47 98.18 0.23 92.49 0.68 91.73 8.37 88.89 0.00 96.90 0.41 94.00 0.57 61.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3677659267
90.24 1.09 98.21 0.03 92.57 0.07 91.73 0.00 88.89 0.00 96.96 0.05 94.14 0.14 69.16 7.33 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.4006227020
91.17 0.94 98.29 0.08 92.62 0.05 92.13 0.39 91.11 2.22 97.01 0.05 94.14 0.00 72.92 3.76 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.108813389
92.00 0.82 98.34 0.05 92.64 0.02 92.13 0.00 93.33 2.22 97.06 0.05 94.14 0.00 76.34 3.42 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1399944166
92.74 0.74 98.34 0.00 92.64 0.00 92.13 0.00 93.33 0.00 97.06 0.00 94.14 0.00 81.53 5.20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2887471892
93.42 0.68 98.35 0.01 92.64 0.00 96.85 4.72 93.33 0.00 97.06 0.00 94.14 0.00 81.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369931258
93.83 0.41 98.35 0.00 92.66 0.01 96.85 0.00 93.33 0.00 97.06 0.00 94.14 0.00 84.41 2.87 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1864603502
94.09 0.26 98.35 0.00 92.66 0.00 96.85 0.00 93.33 0.00 97.06 0.00 94.29 0.14 86.09 1.68 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.627125893
94.32 0.23 98.35 0.00 92.69 0.04 98.03 1.18 93.33 0.00 97.06 0.00 94.43 0.14 86.34 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3467256064
94.52 0.21 98.35 0.00 92.69 0.00 98.03 0.00 93.33 0.00 97.06 0.00 94.43 0.00 87.77 1.44 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3021793177
94.72 0.20 98.35 0.00 92.71 0.01 98.03 0.00 93.33 0.00 97.06 0.00 94.43 0.00 89.16 1.39 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.59036292
94.92 0.19 98.35 0.00 93.48 0.77 98.03 0.00 93.33 0.00 97.09 0.03 94.43 0.00 89.70 0.54 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.963735783
95.09 0.17 98.35 0.00 93.48 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.43 0.00 90.89 1.19 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3307479513
95.22 0.13 98.35 0.00 93.48 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.43 0.00 91.83 0.94 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2048452619
95.34 0.12 98.35 0.00 93.49 0.01 98.03 0.00 93.33 0.00 97.09 0.00 95.29 0.86 91.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3098066392
95.46 0.12 98.35 0.00 93.49 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.29 0.00 92.67 0.84 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2447834474
95.57 0.11 98.35 0.01 93.67 0.19 98.03 0.00 93.33 0.00 97.14 0.05 95.29 0.00 93.17 0.50 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.2000838787
95.67 0.10 98.41 0.06 93.82 0.15 98.43 0.39 93.33 0.00 97.24 0.10 95.29 0.00 93.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3092914145
95.76 0.09 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 93.81 0.64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.614662003
95.84 0.08 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 94.36 0.54 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2811682884
95.90 0.06 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 94.80 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3738267119
95.96 0.06 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 95.20 0.40 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.486877672
96.02 0.06 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 95.59 0.40 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2595527805
96.07 0.05 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.29 0.00 95.94 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3761915461
96.11 0.05 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.14 96.14 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1031603912
96.16 0.04 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.44 0.30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3749025975
96.20 0.04 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.73 0.30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1386759506
96.24 0.04 98.41 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 97.03 0.30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2086686215
96.28 0.04 98.41 0.00 93.87 0.05 98.43 0.00 93.33 0.00 97.28 0.03 95.43 0.00 97.23 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2243659397
96.32 0.04 98.44 0.03 93.91 0.04 98.62 0.20 93.33 0.00 97.28 0.00 95.43 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.1824221323
96.35 0.04 98.44 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.48 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.4009930816
96.39 0.04 98.44 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.72 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.798046563
96.42 0.03 98.44 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.92 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.494330039
96.44 0.02 98.44 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.07 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.583460579
96.46 0.02 98.44 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1764228576
96.48 0.02 98.44 0.00 94.04 0.12 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2737958908
96.49 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.3965928582
96.51 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.2983115096
96.52 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.242848953
96.54 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.4150281287
96.55 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1384371928
96.56 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1130466428
96.58 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.420862772
96.58 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.1206312524
96.59 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.612169208
96.60 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.146265309
96.61 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1184060127
96.61 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2927685702
96.62 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.2417237769
96.63 0.01 98.44 0.00 94.04 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3962032888
96.63 0.01 98.44 0.00 94.06 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2964986620
96.63 0.01 98.44 0.00 94.07 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2768714924
96.63 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.705295290
96.64 0.01 98.44 0.00 94.10 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2931516370

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1720300541
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1673562604
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3544729553
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2636298557
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2724464550
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3234485151
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2010294706
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1075834420
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2963129219
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.322158783
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2655464334
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2766332306
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2681332354
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2344514459
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2195562986
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.442883370
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3198309822
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.1077219478
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1879390118
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1861534380
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.935806018
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.745258405
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2335933863
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3904015526
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.495091667
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.51701508
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.444224025
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.4186148596
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.531780696
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2690867992
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3481640900
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.827368759
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1208550181
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2224173502
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3704055572
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2282489636
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1724609523
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1404358244
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2393775254
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.2811284208
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.3595595807
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2214925775
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.717240555
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3872646046
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1651830913
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3562010863
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.932196969
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1760776166
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3882320406
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2744826712
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2244410874
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.4202610504
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2192987729
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.2483087563
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.644959810
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1066225055
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2590912800
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.688236121
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2040184624
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.67676398
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2970823569
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.61726810
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2741323181
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1603597447
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.424268696
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2627974463
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2518655742
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3533411116
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3836781300
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3680134443
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3693699341
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1095175363
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2039379808
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1052869602
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.426602627
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2477349314
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.902568117
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3667117012
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.879146722
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1288499365
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.915186828
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3554104999
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2267340859
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2565266921
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3015751790
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1047883462
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2776260281
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1558481798
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3134427036
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3856111792



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369931258 Aug 23 10:21:51 PM UTC 24 Aug 23 10:21:53 PM UTC 24 32261082 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2931516370 Aug 23 10:21:51 PM UTC 24 Aug 23 10:21:53 PM UTC 24 41578289 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2210999376 Aug 23 10:21:52 PM UTC 24 Aug 23 10:21:53 PM UTC 24 12302259 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3092914145 Aug 23 10:21:51 PM UTC 24 Aug 23 10:21:54 PM UTC 24 246595212 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3174146145 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:55 PM UTC 24 92546387 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.72389891 Aug 23 10:21:54 PM UTC 24 Aug 23 10:21:56 PM UTC 24 13994801 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.169871208 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:56 PM UTC 24 161548246 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.376120205 Aug 23 10:21:54 PM UTC 24 Aug 23 10:21:56 PM UTC 24 17476046 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3467256064 Aug 23 10:21:54 PM UTC 24 Aug 23 10:21:56 PM UTC 24 75103864 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1725724314 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:56 PM UTC 24 42951273 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2057697044 Aug 23 10:21:54 PM UTC 24 Aug 23 10:21:56 PM UTC 24 38834741 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3668214394 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:58 PM UTC 24 558784343 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.219976973 Aug 23 10:21:56 PM UTC 24 Aug 23 10:21:58 PM UTC 24 357231004 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2843514910 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:59 PM UTC 24 876622086 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.923578562 Aug 23 10:21:53 PM UTC 24 Aug 23 10:21:59 PM UTC 24 529054867 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1293182436 Aug 23 10:21:56 PM UTC 24 Aug 23 10:21:59 PM UTC 24 88728859 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2339798149 Aug 23 10:21:53 PM UTC 24 Aug 23 10:22:00 PM UTC 24 400264776 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2363185567 Aug 23 10:21:55 PM UTC 24 Aug 23 10:22:00 PM UTC 24 4285699534 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.3475086216 Aug 23 10:21:53 PM UTC 24 Aug 23 10:22:02 PM UTC 24 1166795021 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.2000838787 Aug 23 10:21:57 PM UTC 24 Aug 23 10:22:03 PM UTC 24 1420105850 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1909982677 Aug 23 10:21:52 PM UTC 24 Aug 23 10:22:03 PM UTC 24 1386682541 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1555746823 Aug 23 10:21:57 PM UTC 24 Aug 23 10:22:04 PM UTC 24 1386840842 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3677659267 Aug 23 10:22:01 PM UTC 24 Aug 23 10:22:06 PM UTC 24 1509950700 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.486877672 Aug 23 10:21:52 PM UTC 24 Aug 23 10:22:06 PM UTC 24 7548694143 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3707789688 Aug 23 10:22:05 PM UTC 24 Aug 23 10:22:07 PM UTC 24 234648556 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.1824221323 Aug 23 10:22:07 PM UTC 24 Aug 23 10:22:09 PM UTC 24 26011434 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2710211317 Aug 23 10:22:07 PM UTC 24 Aug 23 10:22:09 PM UTC 24 33179812 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3082890784 Aug 23 10:21:58 PM UTC 24 Aug 23 10:22:09 PM UTC 24 547408706 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3642175971 Aug 23 10:22:07 PM UTC 24 Aug 23 10:22:09 PM UTC 24 45847555 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2879311828 Aug 23 10:21:57 PM UTC 24 Aug 23 10:22:11 PM UTC 24 1247156764 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1372774523 Aug 23 10:22:09 PM UTC 24 Aug 23 10:22:12 PM UTC 24 825059423 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1255012140 Aug 23 10:22:10 PM UTC 24 Aug 23 10:22:13 PM UTC 24 69630735 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2983231228 Aug 23 10:22:08 PM UTC 24 Aug 23 10:22:13 PM UTC 24 1481432784 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1997973323 Aug 23 10:22:00 PM UTC 24 Aug 23 10:22:14 PM UTC 24 10232787685 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2357266123 Aug 23 10:22:10 PM UTC 24 Aug 23 10:22:17 PM UTC 24 5455002558 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3085023982 Aug 23 10:21:53 PM UTC 24 Aug 23 10:22:17 PM UTC 24 8559052362 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2060835722 Aug 23 10:22:11 PM UTC 24 Aug 23 10:22:20 PM UTC 24 526599964 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.1945042042 Aug 23 10:22:09 PM UTC 24 Aug 23 10:22:23 PM UTC 24 1962337128 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1549688959 Aug 23 10:22:10 PM UTC 24 Aug 23 10:22:24 PM UTC 24 80715574136 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3721544843 Aug 23 10:22:18 PM UTC 24 Aug 23 10:22:25 PM UTC 24 1842176211 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2634807006 Aug 23 10:22:23 PM UTC 24 Aug 23 10:22:25 PM UTC 24 77832162 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.1620096911 Aug 23 10:22:24 PM UTC 24 Aug 23 10:22:27 PM UTC 24 83208488 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2313576178 Aug 23 10:22:26 PM UTC 24 Aug 23 10:22:28 PM UTC 24 33285525 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2173353161 Aug 23 10:22:14 PM UTC 24 Aug 23 10:22:28 PM UTC 24 1678008024 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3310560679 Aug 23 10:22:26 PM UTC 24 Aug 23 10:22:28 PM UTC 24 18735556 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.943393559 Aug 23 10:22:15 PM UTC 24 Aug 23 10:22:29 PM UTC 24 2047874570 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.1669853592 Aug 23 10:22:27 PM UTC 24 Aug 23 10:22:29 PM UTC 24 15842936 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3230910698 Aug 23 10:21:56 PM UTC 24 Aug 23 10:22:30 PM UTC 24 6320976458 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1992968339 Aug 23 10:22:14 PM UTC 24 Aug 23 10:22:30 PM UTC 24 6496400080 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1870609211 Aug 23 10:22:29 PM UTC 24 Aug 23 10:22:31 PM UTC 24 33019820 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2479161134 Aug 23 10:22:27 PM UTC 24 Aug 23 10:22:33 PM UTC 24 2907600522 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.383014087 Aug 23 10:22:30 PM UTC 24 Aug 23 10:22:33 PM UTC 24 343936982 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4106635122 Aug 23 10:22:30 PM UTC 24 Aug 23 10:22:33 PM UTC 24 1128373091 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.4009930816 Aug 23 10:22:01 PM UTC 24 Aug 23 10:22:34 PM UTC 24 10710524767 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.57609488 Aug 23 10:22:29 PM UTC 24 Aug 23 10:22:35 PM UTC 24 268411573 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2597520838 Aug 23 10:22:31 PM UTC 24 Aug 23 10:22:35 PM UTC 24 236553177 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1706448595 Aug 23 10:22:29 PM UTC 24 Aug 23 10:22:38 PM UTC 24 198515607 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2450837141 Aug 23 10:22:34 PM UTC 24 Aug 23 10:22:39 PM UTC 24 399567401 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1877851047 Aug 23 10:22:34 PM UTC 24 Aug 23 10:22:39 PM UTC 24 99524903 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2811687828 Aug 23 10:22:41 PM UTC 24 Aug 23 10:22:42 PM UTC 24 128866169 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.108813389 Aug 23 10:22:18 PM UTC 24 Aug 23 10:22:43 PM UTC 24 4712841289 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.321476221 Aug 23 10:22:35 PM UTC 24 Aug 23 10:22:44 PM UTC 24 2708329843 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2728430845 Aug 23 10:22:44 PM UTC 24 Aug 23 10:22:45 PM UTC 24 21277142 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3351101785 Aug 23 10:22:44 PM UTC 24 Aug 23 10:22:45 PM UTC 24 12170400 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1597692860 Aug 23 10:22:12 PM UTC 24 Aug 23 10:22:46 PM UTC 24 46989745350 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2918528184 Aug 23 10:22:45 PM UTC 24 Aug 23 10:22:47 PM UTC 24 44152179 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1359726425 Aug 23 10:22:46 PM UTC 24 Aug 23 10:22:47 PM UTC 24 14518915 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3636128012 Aug 23 10:22:47 PM UTC 24 Aug 23 10:22:49 PM UTC 24 345273126 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2767532634 Aug 23 10:22:30 PM UTC 24 Aug 23 10:22:50 PM UTC 24 23753559020 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.1961849219 Aug 23 10:22:48 PM UTC 24 Aug 23 10:22:50 PM UTC 24 17641137 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.453836604 Aug 23 10:21:58 PM UTC 24 Aug 23 10:22:52 PM UTC 24 73285314783 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1492091754 Aug 23 10:22:01 PM UTC 24 Aug 23 10:22:56 PM UTC 24 14146232834 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1279584465 Aug 23 10:22:49 PM UTC 24 Aug 23 10:22:57 PM UTC 24 1492104511 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2216540007 Aug 23 10:22:46 PM UTC 24 Aug 23 10:23:01 PM UTC 24 5389587326 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2908689118 Aug 23 10:22:48 PM UTC 24 Aug 23 10:23:01 PM UTC 24 15582863948 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4288102387 Aug 23 10:22:57 PM UTC 24 Aug 23 10:23:02 PM UTC 24 294162976 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.3288541847 Aug 23 10:22:50 PM UTC 24 Aug 23 10:23:03 PM UTC 24 5266423194 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3346518378 Aug 23 10:22:29 PM UTC 24 Aug 23 10:23:04 PM UTC 24 6631580390 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.1023242030 Aug 23 10:23:02 PM UTC 24 Aug 23 10:23:07 PM UTC 24 219090514 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2326250633 Aug 23 10:22:57 PM UTC 24 Aug 23 10:23:11 PM UTC 24 982675227 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.2448017694 Aug 23 10:23:09 PM UTC 24 Aug 23 10:23:11 PM UTC 24 722343367 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1935517983 Aug 23 10:23:11 PM UTC 24 Aug 23 10:23:13 PM UTC 24 16970714 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1215164722 Aug 23 10:22:04 PM UTC 24 Aug 23 10:23:15 PM UTC 24 7368760180 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3990173946 Aug 23 10:23:13 PM UTC 24 Aug 23 10:23:15 PM UTC 24 45725655 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1227298861 Aug 23 10:23:13 PM UTC 24 Aug 23 10:23:15 PM UTC 24 35270857 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3158429357 Aug 23 10:21:54 PM UTC 24 Aug 23 10:23:16 PM UTC 24 8425854040 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1538306392 Aug 23 10:22:50 PM UTC 24 Aug 23 10:23:18 PM UTC 24 3447617041 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1673795214 Aug 23 10:23:15 PM UTC 24 Aug 23 10:23:19 PM UTC 24 1530688564 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.80562119 Aug 23 10:23:17 PM UTC 24 Aug 23 10:23:19 PM UTC 24 153630925 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.411217649 Aug 23 10:23:15 PM UTC 24 Aug 23 10:23:23 PM UTC 24 1020738494 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.675243350 Aug 23 10:23:20 PM UTC 24 Aug 23 10:23:24 PM UTC 24 1856922515 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.560735979 Aug 23 10:23:18 PM UTC 24 Aug 23 10:23:24 PM UTC 24 672689706 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1859770486 Aug 23 10:23:06 PM UTC 24 Aug 23 10:23:25 PM UTC 24 8535642865 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3689712359 Aug 23 10:22:53 PM UTC 24 Aug 23 10:23:25 PM UTC 24 34931968787 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1981348965 Aug 23 10:23:25 PM UTC 24 Aug 23 10:23:28 PM UTC 24 59731534 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.697830335 Aug 23 10:23:24 PM UTC 24 Aug 23 10:23:29 PM UTC 24 171660776 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.392932751 Aug 23 10:22:39 PM UTC 24 Aug 23 10:23:32 PM UTC 24 87912137839 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.3525443971 Aug 23 10:23:25 PM UTC 24 Aug 23 10:23:33 PM UTC 24 5457208273 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.191945968 Aug 23 10:23:21 PM UTC 24 Aug 23 10:23:34 PM UTC 24 5938738335 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1399944166 Aug 23 10:22:04 PM UTC 24 Aug 23 10:23:34 PM UTC 24 7695936805 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2221883132 Aug 23 10:23:26 PM UTC 24 Aug 23 10:23:35 PM UTC 24 1891736824 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.416227207 Aug 23 10:23:35 PM UTC 24 Aug 23 10:23:37 PM UTC 24 39081460 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.4284239590 Aug 23 10:23:35 PM UTC 24 Aug 23 10:23:37 PM UTC 24 53029882 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.384791398 Aug 23 10:23:21 PM UTC 24 Aug 23 10:23:37 PM UTC 24 2892757546 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1969477590 Aug 23 10:23:35 PM UTC 24 Aug 23 10:23:37 PM UTC 24 26709959 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1208550181 Aug 23 10:23:37 PM UTC 24 Aug 23 10:23:39 PM UTC 24 23686402 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3481640900 Aug 23 10:23:37 PM UTC 24 Aug 23 10:23:41 PM UTC 24 325905855 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2446855129 Aug 23 10:23:25 PM UTC 24 Aug 23 10:23:41 PM UTC 24 2745855582 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.827368759 Aug 23 10:23:38 PM UTC 24 Aug 23 10:23:41 PM UTC 24 57136535 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.444224025 Aug 23 10:23:41 PM UTC 24 Aug 23 10:23:48 PM UTC 24 726830339 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.4186148596 Aug 23 10:23:40 PM UTC 24 Aug 23 10:23:48 PM UTC 24 3841463422 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.180969361 Aug 23 10:23:42 PM UTC 24 Aug 23 10:23:49 PM UTC 24 399202303 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2010302056 Aug 23 10:22:21 PM UTC 24 Aug 23 10:23:53 PM UTC 24 38867632732 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3762766522 Aug 23 10:23:49 PM UTC 24 Aug 23 10:23:55 PM UTC 24 397462747 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2224173502 Aug 23 10:23:49 PM UTC 24 Aug 23 10:23:55 PM UTC 24 2025619977 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.531780696 Aug 23 10:23:56 PM UTC 24 Aug 23 10:24:00 PM UTC 24 303390294 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.713569335 Aug 23 10:23:50 PM UTC 24 Aug 23 10:24:07 PM UTC 24 3127627051 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2447834474 Aug 23 10:23:37 PM UTC 24 Aug 23 10:24:08 PM UTC 24 29096723839 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1347319969 Aug 23 10:23:41 PM UTC 24 Aug 23 10:24:10 PM UTC 24 17573797442 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2898012368 Aug 23 10:23:30 PM UTC 24 Aug 23 10:24:10 PM UTC 24 8841848374 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.3385678355 Aug 23 10:24:11 PM UTC 24 Aug 23 10:24:13 PM UTC 24 47409840 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1724609523 Aug 23 10:24:11 PM UTC 24 Aug 23 10:24:13 PM UTC 24 55631723 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.717240555 Aug 23 10:24:13 PM UTC 24 Aug 23 10:24:15 PM UTC 24 62193078 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1760776166 Aug 23 10:24:13 PM UTC 24 Aug 23 10:24:17 PM UTC 24 292289640 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1704222536 Aug 23 10:22:34 PM UTC 24 Aug 23 10:24:18 PM UTC 24 16050273598 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3021793177 Aug 23 10:22:04 PM UTC 24 Aug 23 10:24:19 PM UTC 24 17442380012 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2744826712 Aug 23 10:24:17 PM UTC 24 Aug 23 10:24:19 PM UTC 24 106862670 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.1206312524 Aug 23 10:22:01 PM UTC 24 Aug 23 10:25:09 PM UTC 24 114476989251 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3882320406 Aug 23 10:24:18 PM UTC 24 Aug 23 10:24:21 PM UTC 24 156381262 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2660351000 Aug 23 10:24:01 PM UTC 24 Aug 23 10:24:21 PM UTC 24 1575993051 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1651830913 Aug 23 10:24:19 PM UTC 24 Aug 23 10:24:24 PM UTC 24 579356052 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.3595595807 Aug 23 10:24:21 PM UTC 24 Aug 23 10:24:26 PM UTC 24 1850213890 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2214925775 Aug 23 10:24:21 PM UTC 24 Aug 23 10:24:28 PM UTC 24 420264507 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2282489636 Aug 23 10:24:26 PM UTC 24 Aug 23 10:24:30 PM UTC 24 46805582 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1326185525 Aug 23 10:23:33 PM UTC 24 Aug 23 10:24:30 PM UTC 24 3843925918 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2244410874 Aug 23 10:24:24 PM UTC 24 Aug 23 10:24:33 PM UTC 24 1670866647 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3562010863 Aug 23 10:24:31 PM UTC 24 Aug 23 10:24:36 PM UTC 24 601764589 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3872646046 Aug 23 10:24:20 PM UTC 24 Aug 23 10:24:36 PM UTC 24 4066284907 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1764228576 Aug 23 10:22:23 PM UTC 24 Aug 23 10:24:37 PM UTC 24 49560319439 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.4006227020 Aug 23 10:23:34 PM UTC 24 Aug 23 10:24:42 PM UTC 24 29284870915 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3704055572 Aug 23 10:24:43 PM UTC 24 Aug 23 10:24:44 PM UTC 24 15486118 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.2483087563 Aug 23 10:24:45 PM UTC 24 Aug 23 10:24:47 PM UTC 24 55013709 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.61726810 Aug 23 10:24:47 PM UTC 24 Aug 23 10:24:49 PM UTC 24 14529466 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1540839938 Aug 23 10:23:54 PM UTC 24 Aug 23 10:24:51 PM UTC 24 4517199070 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2518655742 Aug 23 10:24:50 PM UTC 24 Aug 23 10:24:53 PM UTC 24 458713350 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2811682884 Aug 23 10:23:01 PM UTC 24 Aug 23 10:24:53 PM UTC 24 10959414759 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3836781300 Aug 23 10:24:53 PM UTC 24 Aug 23 10:24:55 PM UTC 24 130544496 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3533411116 Aug 23 10:24:54 PM UTC 24 Aug 23 10:24:56 PM UTC 24 82669918 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.932196969 Aug 23 10:24:16 PM UTC 24 Aug 23 10:24:57 PM UTC 24 15222299370 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.2811284208 Aug 23 10:24:29 PM UTC 24 Aug 23 10:25:00 PM UTC 24 20090205366 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2741323181 Aug 23 10:24:57 PM UTC 24 Aug 23 10:25:01 PM UTC 24 139628673 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.67676398 Aug 23 10:24:58 PM UTC 24 Aug 23 10:25:01 PM UTC 24 55186344 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1603597447 Aug 23 10:24:55 PM UTC 24 Aug 23 10:25:03 PM UTC 24 3999915218 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2393775254 Aug 23 10:24:37 PM UTC 24 Aug 23 10:25:05 PM UTC 24 8448310918 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2192987729 Aug 23 10:25:02 PM UTC 24 Aug 23 10:25:08 PM UTC 24 274721376 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3288285493 Aug 23 10:22:36 PM UTC 24 Aug 23 10:25:09 PM UTC 24 71411517741 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.944240947 Aug 23 10:21:54 PM UTC 24 Aug 23 10:25:11 PM UTC 24 112028837670 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1429744313 Aug 23 10:22:39 PM UTC 24 Aug 23 10:25:12 PM UTC 24 94093565052 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3282754564 Aug 23 10:21:54 PM UTC 24 Aug 23 10:25:12 PM UTC 24 105399340528 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.688236121 Aug 23 10:25:03 PM UTC 24 Aug 23 10:25:13 PM UTC 24 647726317 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.4202610504 Aug 23 10:25:13 PM UTC 24 Aug 23 10:25:14 PM UTC 24 25734500 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2039379808 Aug 23 10:25:14 PM UTC 24 Aug 23 10:25:16 PM UTC 24 24085130 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.915186828 Aug 23 10:25:15 PM UTC 24 Aug 23 10:25:17 PM UTC 24 15608985 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.627125893 Aug 23 10:23:03 PM UTC 24 Aug 23 10:25:18 PM UTC 24 10223230632 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2776260281 Aug 23 10:25:16 PM UTC 24 Aug 23 10:25:19 PM UTC 24 295931536 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2690867992 Aug 23 10:24:09 PM UTC 24 Aug 23 10:25:20 PM UTC 24 6550504210 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3134427036 Aug 23 10:25:19 PM UTC 24 Aug 23 10:25:21 PM UTC 24 53030962 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1558481798 Aug 23 10:25:20 PM UTC 24 Aug 23 10:25:23 PM UTC 24 461084847 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2627974463 Aug 23 10:24:52 PM UTC 24 Aug 23 10:25:24 PM UTC 24 25886788406 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3680134443 Aug 23 10:25:02 PM UTC 24 Aug 23 10:25:26 PM UTC 24 6337835286 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2267340859 Aug 23 10:25:21 PM UTC 24 Aug 23 10:25:27 PM UTC 24 272268369 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.424268696 Aug 23 10:25:09 PM UTC 24 Aug 23 10:25:28 PM UTC 24 1515081609 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3554104999 Aug 23 10:25:21 PM UTC 24 Aug 23 10:25:30 PM UTC 24 847132410 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3856111792 Aug 23 10:25:27 PM UTC 24 Aug 23 10:25:30 PM UTC 24 131260576 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1047883462 Aug 23 10:25:18 PM UTC 24 Aug 23 10:25:32 PM UTC 24 2203294918 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.902568117 Aug 23 10:25:28 PM UTC 24 Aug 23 10:25:33 PM UTC 24 522220348 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3667117012 Aug 23 10:25:31 PM UTC 24 Aug 23 10:25:33 PM UTC 24 50472285 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1095175363 Aug 23 10:25:27 PM UTC 24 Aug 23 10:25:34 PM UTC 24 1957437497 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2565266921 Aug 23 10:25:31 PM UTC 24 Aug 23 10:25:36 PM UTC 24 195569489 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3693699341 Aug 23 10:25:37 PM UTC 24 Aug 23 10:25:38 PM UTC 24 24091432 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1095960099 Aug 23 10:25:39 PM UTC 24 Aug 23 10:25:41 PM UTC 24 21795802 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.879146722 Aug 23 10:25:24 PM UTC 24 Aug 23 10:25:42 PM UTC 24 9634744380 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.31677582 Aug 23 10:25:42 PM UTC 24 Aug 23 10:25:44 PM UTC 24 97495571 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3365105136 Aug 23 10:25:43 PM UTC 24 Aug 23 10:25:45 PM UTC 24 209678322 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3934302683 Aug 23 10:25:46 PM UTC 24 Aug 23 10:25:48 PM UTC 24 517967415 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1983788519 Aug 23 10:25:46 PM UTC 24 Aug 23 10:25:48 PM UTC 24 47433939 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.222018762 Aug 23 10:25:45 PM UTC 24 Aug 23 10:25:52 PM UTC 24 2581645414 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2477349314 Aug 23 10:25:35 PM UTC 24 Aug 23 10:25:54 PM UTC 24 12742978436 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1622800519 Aug 23 10:25:52 PM UTC 24 Aug 23 10:25:55 PM UTC 24 192231252 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4281945422 Aug 23 10:25:48 PM UTC 24 Aug 23 10:25:56 PM UTC 24 959219752 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.407600964 Aug 23 10:25:56 PM UTC 24 Aug 23 10:26:01 PM UTC 24 1395613635 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2727237219 Aug 23 10:25:48 PM UTC 24 Aug 23 10:26:02 PM UTC 24 25308031403 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1844999969 Aug 23 10:25:57 PM UTC 24 Aug 23 10:26:03 PM UTC 24 1199863496 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2590912800 Aug 23 10:25:12 PM UTC 24 Aug 23 10:26:08 PM UTC 24 7063751600 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.146265309 Aug 23 10:26:03 PM UTC 24 Aug 23 10:26:11 PM UTC 24 1067898738 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1947470420 Aug 23 10:26:04 PM UTC 24 Aug 23 10:26:17 PM UTC 24 6568224970 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1288499365 Aug 23 10:25:25 PM UTC 24 Aug 23 10:26:18 PM UTC 24 49542863249 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.342562403 Aug 23 10:23:03 PM UTC 24 Aug 23 10:26:19 PM UTC 24 28484383823 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.2107271977 Aug 23 10:26:19 PM UTC 24 Aug 23 10:26:21 PM UTC 24 63060822 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1471346588 Aug 23 10:25:54 PM UTC 24 Aug 23 10:26:21 PM UTC 24 7806494353 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1179440640 Aug 23 10:23:29 PM UTC 24 Aug 23 10:26:21 PM UTC 24 27224241964 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.401485597 Aug 23 10:26:20 PM UTC 24 Aug 23 10:26:21 PM UTC 24 112488303 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2350440526 Aug 23 10:26:22 PM UTC 24 Aug 23 10:26:24 PM UTC 24 17597803 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2834703718 Aug 23 10:26:22 PM UTC 24 Aug 23 10:26:24 PM UTC 24 256750989 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2469127364 Aug 23 10:26:22 PM UTC 24 Aug 23 10:26:25 PM UTC 24 226376336 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1864603502 Aug 23 10:22:22 PM UTC 24 Aug 23 10:26:25 PM UTC 24 64100969146 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2487123091 Aug 23 10:26:24 PM UTC 24 Aug 23 10:26:26 PM UTC 24 623019361 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.3783162131 Aug 23 10:26:25 PM UTC 24 Aug 23 10:26:27 PM UTC 24 25543087 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1404358244 Aug 23 10:24:34 PM UTC 24 Aug 23 10:26:27 PM UTC 24 15709991712 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.3927534056 Aug 23 10:26:26 PM UTC 24 Aug 23 10:26:31 PM UTC 24 525665467 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3494903610 Aug 23 10:26:25 PM UTC 24 Aug 23 10:26:32 PM UTC 24 1286357985 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2970823569 Aug 23 10:25:00 PM UTC 24 Aug 23 10:26:33 PM UTC 24 30478010846 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2524941011 Aug 23 10:26:22 PM UTC 24 Aug 23 10:26:34 PM UTC 24 20559641815 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.1202542605 Aug 23 10:26:32 PM UTC 24 Aug 23 10:26:36 PM UTC 24 251269290 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1736506576 Aug 23 10:26:27 PM UTC 24 Aug 23 10:26:36 PM UTC 24 442739355 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1031603912 Aug 23 10:22:36 PM UTC 24 Aug 23 10:26:37 PM UTC 24 58226732820 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.644959810 Aug 23 10:25:10 PM UTC 24 Aug 23 10:26:38 PM UTC 24 45811811190 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2469075367 Aug 23 10:26:26 PM UTC 24 Aug 23 10:26:39 PM UTC 24 3411918398 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1407415295 Aug 23 10:26:31 PM UTC 24 Aug 23 10:26:39 PM UTC 24 1121169782 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2040184624 Aug 23 10:25:05 PM UTC 24 Aug 23 10:26:40 PM UTC 24 8090955819 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1433184048 Aug 23 10:26:40 PM UTC 24 Aug 23 10:26:41 PM UTC 24 18722676 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3923220842 Aug 23 10:26:40 PM UTC 24 Aug 23 10:26:41 PM UTC 24 19515891 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3893608838 Aug 23 10:26:27 PM UTC 24 Aug 23 10:26:43 PM UTC 24 919448922 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.621464550 Aug 23 10:26:41 PM UTC 24 Aug 23 10:26:43 PM UTC 24 16454159 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3833375688 Aug 23 10:26:43 PM UTC 24 Aug 23 10:26:45 PM UTC 24 156088553 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3341034686 Aug 23 10:26:43 PM UTC 24 Aug 23 10:26:46 PM UTC 24 232152364 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.240423701 Aug 23 10:26:42 PM UTC 24 Aug 23 10:26:49 PM UTC 24 2488711560 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.59036292 Aug 23 10:21:54 PM UTC 24 Aug 23 10:26:49 PM UTC 24 28898471426 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1983418728 Aug 23 10:26:47 PM UTC 24 Aug 23 10:26:50 PM UTC 24 107548833 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.2333799833 Aug 23 10:26:35 PM UTC 24 Aug 23 10:26:51 PM UTC 24 9960061077 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1859253012 Aug 23 10:26:09 PM UTC 24 Aug 23 10:26:56 PM UTC 24 5114235821 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2476218864 Aug 23 10:26:50 PM UTC 24 Aug 23 10:26:57 PM UTC 24 426163975 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2666128559 Aug 23 10:26:49 PM UTC 24 Aug 23 10:26:58 PM UTC 24 2529446277 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.717717633 Aug 23 10:26:51 PM UTC 24 Aug 23 10:26:58 PM UTC 24 765251904 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2734274822 Aug 23 10:26:57 PM UTC 24 Aug 23 10:27:01 PM UTC 24 39455018 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3922168185 Aug 23 10:26:18 PM UTC 24 Aug 23 10:27:01 PM UTC 24 3223314322 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1695043816 Aug 23 10:26:45 PM UTC 24 Aug 23 10:27:03 PM UTC 24 7242249113 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2149338038 Aug 23 10:23:56 PM UTC 24 Aug 23 10:27:04 PM UTC 24 112115179057 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4042839106 Aug 23 10:26:52 PM UTC 24 Aug 23 10:27:04 PM UTC 24 1817896873 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.1346237798 Aug 23 10:27:04 PM UTC 24 Aug 23 10:27:05 PM UTC 24 63126691 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.2036804689 Aug 23 10:27:05 PM UTC 24 Aug 23 10:27:06 PM UTC 24 65052640 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.323206562 Aug 23 10:27:05 PM UTC 24 Aug 23 10:27:06 PM UTC 24 52698128 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2790094650 Aug 23 10:26:03 PM UTC 24 Aug 23 10:27:07 PM UTC 24 20775875865 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.3398489450 Aug 23 10:27:06 PM UTC 24 Aug 23 10:27:08 PM UTC 24 96007352 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.4123521549 Aug 23 10:27:08 PM UTC 24 Aug 23 10:27:09 PM UTC 24 97699183 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2707031540 Aug 23 10:26:37 PM UTC 24 Aug 23 10:27:10 PM UTC 24 7049520939 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.4062224257 Aug 23 10:26:58 PM UTC 24 Aug 23 10:27:11 PM UTC 24 3068954634 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3860077375 Aug 23 10:26:42 PM UTC 24 Aug 23 10:27:11 PM UTC 24 6023165008 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3978148331 Aug 23 10:27:07 PM UTC 24 Aug 23 10:27:12 PM UTC 24 609114183 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.854984478 Aug 23 10:27:09 PM UTC 24 Aug 23 10:27:12 PM UTC 24 324101432 ps