Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33233	1			T10	18		T16	4		T19	4
auto[SpiFlashAddrCfg]	7415	1			T14	6		T16	4		T23	2
auto[SpiFlashAddr3b]	8870	1			T11	2		T14	2		T16	2
auto[SpiFlashAddr4b]	7348	1			T11	2		T16	4		T19	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33049

1

T10

18

T11

4

T14

8

auto[1]

23817

1

T16

14

T20

2

T54

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31087

1

T10

18

T11

2

T14

4

auto[1]

25779

1

T11

2

T14

4

T16

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37634	1			T10	18		T16	4		T19	4
values[1]	1150	1			T52	2		T57	4		T36	7
values[2]	1414	1			T16	4		T23	2		T55	2
values[3]	1410	1			T14	2		T19	2		T53	4
values[4]	1482	1			T53	4		T62	2		T56	1
values[5]	1361	1			T11	2		T16	2		T53	2
values[6]	1497	1			T14	2		T16	2		T19	2
values[7]	1436	1			T55	8		T59	6		T56	12
values[8]	9482	1			T11	2		T14	4		T16	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29838

1

T10

18

T14

8

T16

14

auto[1]

27028

1

T11

4

T51

3

T140

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53713

1

T10

18

T11

4

T14

8

write

3153

1

T16

4

T23

2

T53

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18434

1

T10

18

T11

4

T14

4

valids[0x1]

38432

1

T14

4

T16

8

T19

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1487	1			T58	2		T110	14		T57	10
internal_process_ops[0x5a]	1579	1			T14	2		T16	2		T23	2
internal_process_ops[0x05]	19833	1			T19	4		T23	76		T58	2
internal_process_ops[0x35]	1502	1			T58	4		T115	2		T61	2
internal_process_ops[0x15]	1503	1			T56	2		T108	2		T109	4
internal_process_ops[0x03]	1077	1			T16	2		T23	4		T54	2
internal_process_ops[0x0b]	988	1			T20	2		T23	2		T54	2
internal_process_ops[0x3b]	1015	1			T19	2		T23	2		T54	2
internal_process_ops[0x6b]	976	1			T19	2		T55	2		T60	2
internal_process_ops[0xbb]	1084	1			T11	2		T14	2		T16	2
internal_process_ops[0xeb]	984	1			T11	2		T14	2		T55	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55347

1

T10

18

T11

4

T14

8

auto[1]

1519

1

T16

4

T56

3

T57

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54610

1

T10

18

T11

4

T14

8

auto[1]

2256

1

T23

2

T56

7

T57

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10389

1

T10

18

T19

4

T23

76

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5808

1

T56

7

T57

22

T37

126

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2025

1

T14

6

T23

2

T53

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1724

1

T16

4

T54

2

T56

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2495

1

T14

2

T19

2

T23

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2040

1

T16

2

T20

2

T54

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2044

1

T19

4

T23

4

T53

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1740

1

T16

4

T54

4

T139

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

157

1

T53

6

T116

2

T184

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T185

1

T186

1

T187

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T37

1

T65

4

T67

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T16

4

T57

2

T37

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T60

2

T57

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

60

1

T57

2

T37

1

T64

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T67

3

T185

1

T188

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T56

1

T37

1

T65

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T61

4

T86

6

T87

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T56

1

T37

1

T65

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T57

1

T37

1

T65

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T56

1

T63

2

T65

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

127

1

T23

2

T57

1

T116

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T37

2

T66

1

T67

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T56

1

T37

2

T66

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

112

1

T57

1

T63

2

T65

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9795

1

T36

354

T49

334

T50

138

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6421

1

T36

115

T49

24

T50

463

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1442

1

T52

3

T36

11

T170

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1477

1

T36

22

T49

18

T50

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1841

1

T11

2

T140

1

T52

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1730

1

T36

22

T49

10

T50

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1379

1

T11

2

T51

3

T52

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1363

1

T36

26

T49

12

T50

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T50

1

T97

2

T189

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T36

7

T50

2

T96

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T36

1

T49

1

T50

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T49

1

T50

1

T190

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T36

1

T49

1

T97

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

113

1

T36

4

T49

6

T50

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T49

2

T50

2

T96

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T36

1

T50

7

T156

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

101

1

T36

1

T49

3

T97

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T49

6

T50

1

T97

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T36

4

T50

2

T39

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T50

3

T39

2

T97

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T49

1

T50

2

T39

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T49

1

T96

3

T190

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T36

1

T49

1

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T36

3

T39

2

T96

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3779	1			T10	18		T23	2		T88	14
auto[0]	values[0]	valids[0x1]	15195	1			T16	4		T19	4		T20	2
auto[0]	values[1]	valids[0x1]	573	1			T57	4		T37	18		T64	4
auto[0]	values[2]	valids[0x0]	560	1			T16	4		T23	2		T55	2
auto[0]	values[2]	valids[0x1]	302	1			T56	2		T57	2		T37	2
auto[0]	values[3]	valids[0x0]	503	1			T14	2		T19	2		T60	2
auto[0]	values[3]	valids[0x1]	294	1			T53	4		T139	2		T56	3
auto[0]	values[4]	valids[0x0]	535	1			T53	4		T62	2		T57	7
auto[0]	values[4]	valids[0x1]	304	1			T56	1		T37	3		T90	4
auto[0]	values[5]	valids[0x0]	464	1			T53	2		T54	2		T56	3
auto[0]	values[5]	valids[0x1]	253	1			T16	2		T59	2		T61	2
auto[0]	values[6]	valids[0x0]	531	1			T19	2		T23	2		T57	4
auto[0]	values[6]	valids[0x1]	350	1			T14	2		T16	2		T54	2
auto[0]	values[7]	valids[0x0]	531	1			T55	4		T59	6		T56	8
auto[0]	values[7]	valids[0x1]	300	1			T55	4		T56	4		T57	1
auto[0]	values[8]	valids[0x0]	3323	1			T14	2		T16	2		T19	2
auto[0]	values[8]	valids[0x1]	2041	1			T14	2		T23	6		T54	2
auto[1]	values[0]	valids[0x0]	3661	1			T36	46		T49	46		T50	63
auto[1]	values[0]	valids[0x1]	14999	1			T52	1		T36	457		T170	1
auto[1]	values[1]	valids[0x1]	577	1			T52	2		T36	7		T49	7
auto[1]	values[2]	valids[0x0]	315	1			T36	5		T50	4		T39	2
auto[1]	values[2]	valids[0x1]	237	1			T36	5		T49	2		T50	2
auto[1]	values[3]	valids[0x0]	323	1			T140	1		T36	4		T49	4
auto[1]	values[3]	valids[0x1]	290	1			T36	1		T49	5		T50	8
auto[1]	values[4]	valids[0x0]	410	1			T36	3		T170	1		T49	6
auto[1]	values[4]	valids[0x1]	233	1			T36	3		T49	2		T50	1
auto[1]	values[5]	valids[0x0]	381	1			T11	2		T36	13		T170	1
auto[1]	values[5]	valids[0x1]	263	1			T124	2		T49	1		T50	4
auto[1]	values[6]	valids[0x0]	361	1			T51	3		T52	1		T36	8
auto[1]	values[6]	valids[0x1]	255	1			T36	4		T49	2		T50	5
auto[1]	values[7]	valids[0x0]	338	1			T124	2		T36	9		T97	5
auto[1]	values[7]	valids[0x1]	267	1			T36	3		T49	4		T50	4
auto[1]	values[8]	valids[0x0]	2419	1			T11	2		T52	3		T36	29
auto[1]	values[8]	valids[0x1]	1699	1			T124	1		T36	23		T170	1