Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3319691

1

T7

1

T10

18

T11

674

auto[1]

36069

1

T23

76

T56

233

T57

507

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

997215

1

T7

1

T10

18

T11

674

auto[1]

2358545

1

T23

76

T59

5324

T62

512

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	620841	1			T7	1		T10	4		T11	4
auto[524288:1048575]	387143	1			T11	77		T19	9		T88	1192
auto[1048576:1572863]	426544	1			T18	188		T19	112		T88	10
auto[1572864:2097151]	393106	1			T18	990		T19	77		T88	7
auto[2097152:2621439]	338979	1			T10	4		T11	507		T19	338
auto[2621440:3145727]	394934	1			T11	31		T18	199		T19	90
auto[3145728:3670015]	386534	1			T10	10		T11	55		T19	2
auto[3670016:4194303]	407679	1			T19	81		T88	2148		T58	386

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392821

1

T7

1

T10

18

T11

12

auto[1]

962939

1

T11

662

T18

2567

T19

823

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2867148

1

T7

1

T10

15

T11

674

auto[1]

488612

1

T10

3

T88

1576

T91

138

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	234061	1			T7	1		T10	4		T11	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	326111	1			T23	2		T59	5324		T62	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	84347	1			T11	77		T19	9		T88	1183
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	247607	1			T56	2625		T108	250		T57	2906
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	136172	1			T18	188		T19	112		T88	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	224543	1			T108	7		T57	265		T184	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	133325	1			T18	990		T19	77		T88	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	180844	1			T108	2962		T57	2995		T184	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	78086	1			T10	1		T11	507		T19	338
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	200525	1			T56	256		T57	512		T36	1159
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	108779	1			T11	31		T18	199		T19	90
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	231109	1			T108	2956		T57	514		T184	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	81180	1			T10	10		T11	55		T19	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	230326	1			T57	4		T184	173		T36	73
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	123744	1			T19	81		T88	2148		T58	386
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	218061	1			T56	256		T57	256		T36	6
auto[0]	auto[1]	auto[0:524287]	auto[0]	2137	1			T88	767		T91	1		T36	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	54029	1			T36	3		T65	291		T50	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	689	1			T88	9		T91	20		T56	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49786	1			T36	2		T65	6		T67	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1611	1			T88	8		T91	1		T56	16
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60191	1			T56	256		T37	2742		T49	2880
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1382	1			T88	3		T56	2		T57	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	73260	1			T37	2		T66	5		T49	2112
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2670	1			T10	3		T88	788		T56	17
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53396	1			T57	3		T50	992		T187	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	954	1			T88	1		T56	5		T57	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49977	1			T36	2999		T64	2820		T49	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2968	1			T91	1		T56	22		T57	22
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	68464	1			T57	98		T37	70		T49	1075
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1143	1			T91	115		T56	2		T57	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58214	1			T66	261		T49	106		T39	109
auto[1]	auto[0]	auto[0:524287]	auto[0]	564	1			T23	2		T57	10		T36	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	3312	1			T23	74		T57	22		T36	129
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	423	1			T56	28		T57	9		T66	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2922	1			T56	194		T66	22		T49	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	375	1			T57	7		T36	3		T37	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2500	1			T36	28		T37	22		T65	70
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	404	1			T56	3		T57	16		T36	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2486	1			T57	256		T36	7		T37	12
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	403	1			T57	5		T36	4		T37	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3105	1			T36	63		T37	31		T49	63
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	452	1			T56	5		T36	1		T37	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3331	1			T36	9		T37	46		T65	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	304	1			T57	16		T36	1		T37	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2618	1			T36	21		T37	112		T64	20
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	350	1			T57	5		T36	1		T37	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4779	1			T36	52		T37	36		T65	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	138	1			T36	3		T65	1		T50	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	489	1			T36	53		T65	15		T50	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	104	1			T65	2		T67	2		T97	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1265	1			T65	28		T67	35		T97	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	63	1			T50	8		T96	1		T154	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1089	1			T50	218		T96	9		T154	24
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	84	1			T37	2		T49	1		T200	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1321	1			T37	68		T263	1		T264	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	74	1			T187	3		T96	1		T190	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	720	1			T96	18		T190	64		T40	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	47	1			T187	6		T97	2		T154	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	285	1			T97	1		T154	13		T156	22
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	104	1			T56	3		T57	3		T49	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	570	1			T57	158		T49	1		T67	27
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T97	1		T154	1		T156	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1310	1			T97	3		T154	1		T156	13

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1885160	1			T7	1		T10	15		T11	12
auto[0]	auto[0]	auto[1]	953660	1			T11	662		T18	2567		T19	823
auto[0]	auto[1]	auto[0]	472285	1			T10	3		T88	10		T91	7
auto[0]	auto[1]	auto[1]	8586	1			T88	1566		T91	131		T36	1
auto[1]	auto[0]	auto[0]	27762	1			T23	76		T56	225		T57	337
auto[1]	auto[0]	auto[1]	566	1			T56	5		T57	9		T36	2
auto[1]	auto[1]	auto[0]	7614	1			T56	2		T57	160		T36	55
auto[1]	auto[1]	auto[1]	127	1			T56	1		T57	1		T36	1