Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2632494	1			T1	1		T2	1		T3	1
all_pins[1]	2632494	1			T1	1		T2	1		T3	1
all_pins[2]	2632494	1			T1	1		T2	1		T3	1
all_pins[3]	2632494	1			T1	1		T2	1		T3	1
all_pins[4]	2632494	1			T1	1		T2	1		T3	1
all_pins[5]	2632494	1			T1	1		T2	1		T3	1
all_pins[6]	2632494	1			T1	1		T2	1		T3	1
all_pins[7]	2632494	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21050401	1			T1	8		T2	8		T3	8
values[0x1]	9551	1			T24	36		T37	178		T38	8
transitions[0x0=>0x1]	8807	1			T24	31		T37	115		T38	8
transitions[0x1=>0x0]	8823	1			T24	32		T37	115		T38	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2631816	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	678	1			T24	6		T37	103		T38	3
all_pins[0]	transitions[0x0=>0x1]	327	1			T24	6		T37	45		T38	3
all_pins[0]	transitions[0x1=>0x0]	246	1			T24	3		T39	2		T96	1
all_pins[1]	values[0x0]	2631897	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	597	1			T24	3		T37	58		T39	2
all_pins[1]	transitions[0x0=>0x1]	523	1			T24	3		T37	54		T39	1
all_pins[1]	transitions[0x1=>0x0]	222	1			T24	2		T37	4		T39	4
all_pins[2]	values[0x0]	2632198	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	296	1			T24	2		T37	8		T39	5
all_pins[2]	transitions[0x0=>0x1]	223	1			T24	1		T37	8		T39	1
all_pins[2]	transitions[0x1=>0x0]	142	1			T24	3		T39	2		T96	2
all_pins[3]	values[0x0]	2632279	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	215	1			T24	4		T39	6		T96	4
all_pins[3]	transitions[0x0=>0x1]	176	1			T24	3		T39	4		T96	4
all_pins[3]	transitions[0x1=>0x0]	156	1			T24	6		T37	3		T38	2
all_pins[4]	values[0x0]	2632299	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	195	1			T24	7		T37	3		T38	2
all_pins[4]	transitions[0x0=>0x1]	158	1			T24	6		T37	3		T38	2
all_pins[4]	transitions[0x1=>0x0]	918	1			T24	4		T37	2		T96	4
all_pins[5]	values[0x0]	2631539	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	955	1			T24	5		T37	2		T96	4
all_pins[5]	transitions[0x0=>0x1]	902	1			T24	4		T37	2		T96	2
all_pins[5]	transitions[0x1=>0x0]	6353	1			T24	4		T37	3		T39	2
all_pins[6]	values[0x0]	2626088	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	6406	1			T24	5		T37	3		T39	2
all_pins[6]	transitions[0x0=>0x1]	6350	1			T24	5		T37	2		T39	2
all_pins[6]	transitions[0x1=>0x0]	153	1			T24	4		T38	3		T175	2
all_pins[7]	values[0x0]	2632285	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	209	1			T24	4		T37	1		T38	3
all_pins[7]	transitions[0x0=>0x1]	148	1			T24	3		T37	1		T38	3
all_pins[7]	transitions[0x1=>0x0]	633	1			T24	6		T37	103		T38	3