Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17789

1

T10

18

T14

8

T19

10

auto[1]

12049

1

T16

14

T20

2

T54

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3376	1			T19	10		T20	2		T60	12
values[1]	3866	1			T88	14		T91	8		T56	40
values[2]	2864	1			T16	14		T265	20		T65	67
values[3]	4158	1			T55	24		T109	18		T57	60
values[4]	3579	1			T58	10		T61	14		T37	20
values[5]	3830	1			T10	18		T62	16		T56	40
values[6]	3994	1			T23	102		T54	8		T115	4
values[7]	4171	1			T14	8		T53	18		T59	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3755	1			T20	2		T61	14		T56	20
values[1]	3526	1			T54	8		T58	10		T115	4
values[2]	4115	1			T19	10		T88	14		T62	16
values[3]	3635	1			T23	102		T110	14		T57	80
values[4]	3716	1			T16	14		T59	20		T65	40
values[5]	3360	1			T91	8		T57	20		T37	250
values[6]	3935	1			T55	24		T56	20		T63	18
values[7]	3796	1			T10	18		T14	8		T53	18

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	240	1			T232	18		T188	7		T244	9
auto[0]	values[0]	values[1]	172	1			T65	14		T67	7		T187	17
auto[0]	values[0]	values[2]	220	1			T19	10		T266	4		T187	11
auto[0]	values[0]	values[3]	203	1			T110	14		T154	13		T267	12
auto[0]	values[0]	values[4]	214	1			T80	11		T216	13		T237	11
auto[0]	values[0]	values[5]	170	1			T64	11		T187	7		T268	8
auto[0]	values[0]	values[6]	183	1			T92	10		T187	11		T183	15
auto[0]	values[0]	values[7]	370	1			T60	12		T65	107		T269	12
auto[0]	values[1]	values[0]	259	1			T56	15		T90	16		T257	41
auto[0]	values[1]	values[1]	454	1			T108	4		T66	105		T185	11
auto[0]	values[1]	values[2]	346	1			T88	14		T56	10		T87	55
auto[0]	values[1]	values[3]	211	1			T37	12		T270	2		T67	50
auto[0]	values[1]	values[4]	212	1			T261	6		T66	49		T47	8
auto[0]	values[1]	values[5]	217	1			T91	8		T47	10		T188	20
auto[0]	values[1]	values[6]	233	1			T271	8		T233	22		T177	11
auto[0]	values[1]	values[7]	296	1			T227	17		T183	35		T272	22
auto[0]	values[2]	values[0]	179	1			T154	18		T40	24		T41	9
auto[0]	values[2]	values[1]	198	1			T273	6		T274	10		T275	18
auto[0]	values[2]	values[2]	157	1			T67	9		T223	11		T216	13
auto[0]	values[2]	values[3]	121	1			T187	11		T276	4		T277	7
auto[0]	values[2]	values[4]	284	1			T278	4		T185	11		T256	16
auto[0]	values[2]	values[5]	160	1			T265	20		T279	2		T263	7
auto[0]	values[2]	values[6]	282	1			T65	57		T154	23		T280	14
auto[0]	values[2]	values[7]	350	1			T67	11		T241	13		T239	18
auto[0]	values[3]	values[0]	244	1			T47	10		T231	2		T40	22
auto[0]	values[3]	values[1]	306	1			T109	18		T219	16		T154	13
auto[0]	values[3]	values[2]	384	1			T57	12		T37	11		T64	13
auto[0]	values[3]	values[3]	316	1			T57	10		T154	9		T281	14
auto[0]	values[3]	values[4]	336	1			T67	11		T40	11		T240	16
auto[0]	values[3]	values[5]	475	1			T57	12		T37	151		T187	12
auto[0]	values[3]	values[6]	326	1			T55	24		T225	13		T282	10
auto[0]	values[3]	values[7]	110	1			T227	14		T283	4		T209	17
auto[0]	values[4]	values[0]	314	1			T61	14		T154	17		T284	17
auto[0]	values[4]	values[1]	90	1			T58	10		T250	15		T216	11
auto[0]	values[4]	values[2]	469	1			T161	14		T177	59		T114	15
auto[0]	values[4]	values[3]	269	1			T37	14		T65	8		T242	10
auto[0]	values[4]	values[4]	296	1			T67	14		T223	13		T285	2
auto[0]	values[4]	values[5]	201	1			T227	52		T208	16		T286	10
auto[0]	values[4]	values[6]	394	1			T86	91		T223	25		T77	90
auto[0]	values[4]	values[7]	241	1			T287	4		T186	5		T154	35
auto[0]	values[5]	values[0]	247	1			T37	44		T65	10		T67	10
auto[0]	values[5]	values[1]	367	1			T56	12		T188	13		T288	28
auto[0]	values[5]	values[2]	192	1			T62	16		T186	15		T80	14
auto[0]	values[5]	values[3]	422	1			T57	23		T116	20		T37	9
auto[0]	values[5]	values[4]	395	1			T187	15		T80	8		T225	10
auto[0]	values[5]	values[5]	133	1			T289	10		T223	12		T77	12
auto[0]	values[5]	values[6]	256	1			T56	16		T230	12		T40	26
auto[0]	values[5]	values[7]	319	1			T10	18		T37	50		T241	11
auto[0]	values[6]	values[0]	203	1			T243	16		T80	12		T114	14
auto[0]	values[6]	values[1]	386	1			T115	4		T57	12		T37	28
auto[0]	values[6]	values[2]	341	1			T65	15		T66	84		T185	11
auto[0]	values[6]	values[3]	426	1			T23	102		T89	13		T227	117
auto[0]	values[6]	values[4]	192	1			T65	20		T67	8		T186	10
auto[0]	values[6]	values[5]	395	1			T37	82		T187	12		T227	13
auto[0]	values[6]	values[6]	262	1			T188	14		T223	15		T225	15
auto[0]	values[6]	values[7]	324	1			T57	11		T111	2		T64	8
auto[0]	values[7]	values[0]	355	1			T188	12		T154	32		T247	8
auto[0]	values[7]	values[1]	267	1			T185	11		T227	12		T183	13
auto[0]	values[7]	values[2]	461	1			T56	11		T290	2		T188	11
auto[0]	values[7]	values[3]	184	1			T57	9		T40	8		T251	11
auto[0]	values[7]	values[4]	246	1			T59	20		T183	9		T245	40
auto[0]	values[7]	values[5]	191	1			T225	29		T208	13		T245	68
auto[0]	values[7]	values[6]	265	1			T37	13		T66	13		T223	11
auto[0]	values[7]	values[7]	458	1			T14	8		T53	18		T102	2
auto[1]	values[0]	values[0]	262	1			T20	2		T188	16		T244	11
auto[1]	values[0]	values[1]	207	1			T65	46		T67	23		T187	3
auto[1]	values[0]	values[2]	141	1			T215	16		T187	9		T257	1
auto[1]	values[0]	values[3]	131	1			T154	49		T208	9		T245	3
auto[1]	values[0]	values[4]	100	1			T80	9		T216	7		T237	9
auto[1]	values[0]	values[5]	128	1			T64	9		T187	13		T245	6
auto[1]	values[0]	values[6]	284	1			T187	9		T183	5		T233	10
auto[1]	values[0]	values[7]	351	1			T65	21		T244	8		T260	10
auto[1]	values[1]	values[0]	185	1			T56	5		T257	9		T177	6
auto[1]	values[1]	values[1]	179	1			T291	18		T66	10		T185	9
auto[1]	values[1]	values[2]	198	1			T56	10		T186	7		T188	10
auto[1]	values[1]	values[3]	226	1			T37	8		T67	7		T223	42
auto[1]	values[1]	values[4]	165	1			T66	19		T47	12		T245	12
auto[1]	values[1]	values[5]	325	1			T47	10		T188	122		T225	12
auto[1]	values[1]	values[6]	159	1			T233	41		T177	9		T240	9
auto[1]	values[1]	values[7]	201	1			T227	3		T183	8		T221	8
auto[1]	values[2]	values[0]	208	1			T154	13		T40	5		T41	11
auto[1]	values[2]	values[1]	125	1			T273	19		T292	6		T274	10
auto[1]	values[2]	values[2]	63	1			T67	11		T223	9		T216	8
auto[1]	values[2]	values[3]	139	1			T187	9		T293	2		T277	14
auto[1]	values[2]	values[4]	137	1			T16	14		T185	18		T256	4
auto[1]	values[2]	values[5]	199	1			T249	18		T263	13		T294	7
auto[1]	values[2]	values[6]	105	1			T65	10		T154	10		T240	2
auto[1]	values[2]	values[7]	157	1			T67	20		T241	7		T245	13
auto[1]	values[3]	values[0]	193	1			T47	10		T40	23		T295	24
auto[1]	values[3]	values[1]	128	1			T154	7		T177	9		T240	8
auto[1]	values[3]	values[2]	288	1			T57	8		T37	9		T64	7
auto[1]	values[3]	values[3]	238	1			T57	10		T154	48		T216	20
auto[1]	values[3]	values[4]	231	1			T67	9		T40	9		T240	42
auto[1]	values[3]	values[5]	171	1			T57	8		T37	11		T187	8
auto[1]	values[3]	values[6]	318	1			T225	18		T183	8		T233	25
auto[1]	values[3]	values[7]	94	1			T235	20		T227	6		T209	3
auto[1]	values[4]	values[0]	183	1			T154	7		T251	5		T41	9
auto[1]	values[4]	values[1]	62	1			T296	12		T250	5		T216	12
auto[1]	values[4]	values[2]	246	1			T177	13		T114	5		T209	7
auto[1]	values[4]	values[3]	156	1			T37	6		T65	12		T80	8
auto[1]	values[4]	values[4]	169	1			T67	8		T223	35		T233	15
auto[1]	values[4]	values[5]	170	1			T227	3		T208	5		T210	20
auto[1]	values[4]	values[6]	197	1			T223	16		T77	9		T80	6
auto[1]	values[4]	values[7]	122	1			T186	15		T154	9		T211	10
auto[1]	values[5]	values[0]	272	1			T37	10		T65	10		T67	55
auto[1]	values[5]	values[1]	160	1			T56	8		T188	7		T183	8
auto[1]	values[5]	values[2]	137	1			T186	5		T80	6		T40	10
auto[1]	values[5]	values[3]	159	1			T57	17		T37	11		T80	11
auto[1]	values[5]	values[4]	311	1			T187	5		T80	12		T225	10
auto[1]	values[5]	values[5]	188	1			T223	9		T77	8		T245	45
auto[1]	values[5]	values[6]	170	1			T56	4		T63	18		T40	24
auto[1]	values[5]	values[7]	102	1			T37	13		T241	10		T188	10
auto[1]	values[6]	values[0]	127	1			T297	16		T80	8		T114	6
auto[1]	values[6]	values[1]	280	1			T54	8		T57	8		T37	5
auto[1]	values[6]	values[2]	128	1			T65	5		T66	7		T185	9
auto[1]	values[6]	values[3]	178	1			T89	7		T227	10		T40	20
auto[1]	values[6]	values[4]	212	1			T65	20		T67	54		T186	10
auto[1]	values[6]	values[5]	132	1			T37	6		T187	8		T227	17
auto[1]	values[6]	values[6]	191	1			T188	6		T163	10		T223	5
auto[1]	values[6]	values[7]	217	1			T57	9		T64	33		T187	6
auto[1]	values[7]	values[0]	284	1			T188	8		T154	22		T247	12
auto[1]	values[7]	values[1]	145	1			T139	2		T185	9		T227	18
auto[1]	values[7]	values[2]	344	1			T56	9		T188	9		T227	9
auto[1]	values[7]	values[3]	256	1			T57	11		T78	24		T40	12
auto[1]	values[7]	values[4]	216	1			T183	46		T245	4		T233	42
auto[1]	values[7]	values[5]	105	1			T225	3		T208	7		T245	10
auto[1]	values[7]	values[6]	310	1			T37	114		T66	7		T223	16
auto[1]	values[7]	values[7]	84	1			T188	11		T177	10		T42	16