Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	347	1			T19	4		T56	5		T57	4
auto[ReadAddrCrossIntoMailbox]	265	1			T56	2		T57	3		T37	4
auto[ReadAddrCrossOutOfMailbox]	245	1			T56	5		T57	3		T37	4
auto[ReadAddrCrossAllMailbox]	180	1			T56	1		T57	2		T37	1
auto[ReadAddrOutsideMailbox]	3571	1			T14	4		T16	4		T19	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307

1

T14

2

T16

2

T19

3

auto[1]

2301

1

T14

2

T16

2

T19

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	803	1			T16	2		T23	4		T54	2
read_ops[0x0b]	724	1			T20	2		T23	2		T54	2
read_ops[0x3b]	765	1			T19	2		T23	2		T54	2
read_ops[0x6b]	746	1			T19	2		T55	2		T60	2
read_ops[0xbb]	830	1			T14	2		T16	2		T19	2
read_ops[0xeb]	740	1			T14	2		T55	2		T62	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T184	1		T66	1		T227	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T184	1		T185	2		T83	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T57	1		T298	1		T223	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T37	1		T66	1		T154	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T57	1		T37	1		T154	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T56	3		T64	1		T186	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T37	1		T245	1		T233	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T57	1		T227	1		T42	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T16	1		T23	2		T54	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T16	1		T23	2		T54	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T184	1		T66	1		T47	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T56	3		T57	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T66	1		T288	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T56	1		T241	1		T288	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T37	1		T64	2		T154	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T37	1		T223	1		T245	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T298	1		T80	1		T251	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T298	1		T223	1		T299	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T20	1		T23	1		T54	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T20	1		T23	1		T54	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T19	1		T57	1		T184	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T19	1		T184	2		T219	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T37	1		T64	1		T187	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T37	1		T185	1		T227	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T67	1		T185	1		T80	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T65	1		T227	1		T114	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T57	1		T300	1		T294	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T300	1		T209	2		T250	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T23	1		T54	1		T55	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T23	1		T54	1		T55	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T67	1		T48	1		T227	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T57	1		T47	1		T67	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T65	1		T67	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T57	1		T37	1		T65	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	10	1			T186	1		T227	1		T80	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T57	1		T66	1		T227	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T288	1		T301	2		T245	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T56	1		T65	1		T187	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T19	1		T55	1		T60	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T19	1		T55	1		T60	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T19	1		T56	1		T288	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T19	1		T56	1		T241	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T57	1		T67	1		T298	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T56	1		T67	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T57	1		T186	1		T227	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T56	2		T241	1		T227	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T298	1		T288	1		T223	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T298	1		T288	1		T302	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T14	1		T16	1		T53	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T14	1		T16	1		T53	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T261	1		T67	1		T223	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T57	1		T37	1		T261	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T67	1		T186	2		T233	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T65	1		T66	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T37	1		T261	1		T257	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T261	1		T188	1		T83	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T227	1		T154	1		T223	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T185	2		T223	2		T263	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T14	1		T55	1		T62	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T14	1		T55	1		T62	1