Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3749	1			T62	16		T110	14		T57	80
values[1]	3331	1			T19	10		T23	102		T57	20
values[2]	4219	1			T53	18		T115	4		T56	80
values[3]	3638	1			T20	2		T63	18		T116	20
values[4]	3285	1			T10	18		T88	14		T58	10
values[5]	4260	1			T86	91		T187	40		T271	8
values[6]	3715	1			T14	8		T55	24		T102	2
values[7]	3641	1			T16	14		T54	8		T60	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4407	1			T19	10		T23	102		T109	18
values[1]	3685	1			T53	18		T62	16		T57	20
values[2]	3757	1			T16	14		T55	24		T60	12
values[3]	3617	1			T58	10		T56	40		T110	14
values[4]	4029	1			T10	18		T14	8		T88	14
values[5]	3686	1			T20	2		T59	20		T61	14
values[6]	3379	1			T54	8		T115	4		T139	2
values[7]	3278	1			T102	2		T56	20		T265	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29099

1

T10

18

T14

8

T16

10

auto[1]

739

1

T16

4

T56

3

T57

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	320	1			T80	20		T40	20		T208	18
auto[0]	values[0]	values[1]	463	1			T62	16		T80	20		T225	31
auto[0]	values[0]	values[2]	502	1			T57	18		T185	20		T187	20
auto[0]	values[0]	values[3]	501	1			T110	14		T37	43		T227	20
auto[0]	values[0]	values[4]	381	1			T57	20		T65	20		T67	65
auto[0]	values[0]	values[5]	334	1			T57	40		T266	4		T188	18
auto[0]	values[0]	values[6]	596	1			T67	30		T188	50		T257	20
auto[0]	values[0]	values[7]	550	1			T265	20		T66	90		T47	20
auto[0]	values[1]	values[0]	686	1			T19	10		T23	102		T57	17
auto[0]	values[1]	values[1]	419	1			T64	20		T259	8		T233	39
auto[0]	values[1]	values[2]	264	1			T65	18		T66	20		T40	26
auto[0]	values[1]	values[3]	442	1			T65	65		T186	20		T241	21
auto[0]	values[1]	values[4]	495	1			T65	59		T219	16		T243	16
auto[0]	values[1]	values[5]	249	1			T303	8		T245	94		T263	21
auto[0]	values[1]	values[6]	367	1			T92	10		T37	19		T185	28
auto[0]	values[1]	values[7]	314	1			T187	18		T231	2		T80	20
auto[0]	values[2]	values[0]	551	1			T66	47		T242	10		T186	19
auto[0]	values[2]	values[1]	577	1			T53	18		T57	20		T87	55
auto[0]	values[2]	values[2]	620	1			T261	6		T223	31		T79	2
auto[0]	values[2]	values[3]	682	1			T56	39		T37	162		T187	19
auto[0]	values[2]	values[4]	532	1			T56	19		T184	18		T270	2
auto[0]	values[2]	values[5]	309	1			T56	20		T187	20		T241	20
auto[0]	values[2]	values[6]	405	1			T115	4		T37	87		T288	28
auto[0]	values[2]	values[7]	420	1			T67	62		T208	20		T304	18
auto[0]	values[3]	values[0]	376	1			T116	20		T112	10		T89	20
auto[0]	values[3]	values[1]	498	1			T37	20		T67	22		T80	20
auto[0]	values[3]	values[2]	344	1			T63	14		T65	35		T154	34
auto[0]	values[3]	values[3]	253	1			T37	20		T154	62		T305	4
auto[0]	values[3]	values[4]	332	1			T232	18		T77	99		T183	19
auto[0]	values[3]	values[5]	585	1			T20	2		T188	95		T257	50
auto[0]	values[3]	values[6]	609	1			T64	40		T297	16		T187	20
auto[0]	values[3]	values[7]	566	1			T223	50		T246	18		T240	37
auto[0]	values[4]	values[0]	682	1			T37	51		T66	115		T227	20
auto[0]	values[4]	values[1]	218	1			T215	16		T249	16		T233	32
auto[0]	values[4]	values[2]	490	1			T187	19		T80	20		T225	20
auto[0]	values[4]	values[3]	318	1			T58	10		T111	2		T187	20
auto[0]	values[4]	values[4]	422	1			T10	18		T88	14		T91	8
auto[0]	values[4]	values[5]	377	1			T279	2		T177	22		T240	45
auto[0]	values[4]	values[6]	383	1			T67	20		T187	18		T223	26
auto[0]	values[4]	values[7]	323	1			T188	39		T301	8		T177	26
auto[0]	values[5]	values[0]	521	1			T306	6		T233	23		T177	50
auto[0]	values[5]	values[1]	520	1			T80	20		T177	41		T41	21
auto[0]	values[5]	values[2]	537	1			T177	21		T234	26		T294	23
auto[0]	values[5]	values[3]	389	1			T227	51		T220	14		T233	20
auto[0]	values[5]	values[4]	839	1			T187	40		T271	8		T227	53
auto[0]	values[5]	values[5]	609	1			T86	91		T257	117		T80	19
auto[0]	values[5]	values[6]	321	1			T307	14		T183	20		T245	20
auto[0]	values[5]	values[7]	429	1			T154	23		T308	22		T283	4
auto[0]	values[6]	values[0]	659	1			T109	18		T47	19		T48	2
auto[0]	values[6]	values[1]	534	1			T64	20		T154	55		T40	22
auto[0]	values[6]	values[2]	391	1			T55	24		T185	20		T187	20
auto[0]	values[6]	values[3]	438	1			T65	20		T154	19		T80	20
auto[0]	values[6]	values[4]	474	1			T14	8		T40	23		T245	50
auto[0]	values[6]	values[5]	651	1			T61	14		T57	20		T37	54
auto[0]	values[6]	values[6]	286	1			T139	2		T67	19		T183	20
auto[0]	values[6]	values[7]	196	1			T102	2		T287	4		T67	40
auto[0]	values[7]	values[0]	506	1			T37	123		T67	55		T183	43
auto[0]	values[7]	values[1]	363	1			T186	20		T154	29		T177	19
auto[0]	values[7]	values[2]	506	1			T16	10		T60	12		T108	4
auto[0]	values[7]	values[3]	506	1			T223	48		T40	20		T233	20
auto[0]	values[7]	values[4]	450	1			T57	20		T67	28		T269	12
auto[0]	values[7]	values[5]	474	1			T59	20		T309	6		T223	21
auto[0]	values[7]	values[6]	336	1			T54	8		T177	20		T251	20
auto[0]	values[7]	values[7]	409	1			T56	19		T235	18		T245	20
auto[1]	values[0]	values[0]	8	1			T208	2		T310	2		T311	1
auto[1]	values[0]	values[1]	13	1			T225	1		T312	2		T277	1
auto[1]	values[0]	values[2]	18	1			T57	2		T223	4		T260	1
auto[1]	values[0]	values[3]	7	1			T313	1		T314	1		T315	2
auto[1]	values[0]	values[4]	13	1			T186	2		T114	1		T221	4
auto[1]	values[0]	values[5]	12	1			T188	4		T183	1		T312	1
auto[1]	values[0]	values[6]	17	1			T67	1		T114	1		T247	2
auto[1]	values[0]	values[7]	14	1			T66	1		T210	1		T224	2
auto[1]	values[1]	values[0]	26	1			T57	3		T209	2		T237	2
auto[1]	values[1]	values[1]	8	1			T233	4		T42	1		T273	3
auto[1]	values[1]	values[2]	6	1			T65	2		T40	2		T316	1
auto[1]	values[1]	values[3]	16	1			T65	2		T251	3		T42	2
auto[1]	values[1]	values[4]	11	1			T65	1		T40	2		T42	1
auto[1]	values[1]	values[5]	10	1			T245	4		T263	2		T41	2
auto[1]	values[1]	values[6]	10	1			T37	1		T185	1		T224	4
auto[1]	values[1]	values[7]	8	1			T187	2		T317	1		T318	1
auto[1]	values[2]	values[0]	14	1			T66	1		T186	1		T154	2
auto[1]	values[2]	values[1]	27	1			T65	1		T187	2		T216	2
auto[1]	values[2]	values[2]	20	1			T319	2		T320	4		T316	4
auto[1]	values[2]	values[3]	15	1			T56	1		T187	1		T40	3
auto[1]	values[2]	values[4]	18	1			T56	1		T227	5		T208	5
auto[1]	values[2]	values[5]	10	1			T188	2		T223	2		T250	2
auto[1]	values[2]	values[6]	10	1			T37	1		T321	3		T322	1
auto[1]	values[2]	values[7]	9	1			T183	3		T221	1		T216	1
auto[1]	values[3]	values[0]	7	1			T188	2		T80	1		T183	2
auto[1]	values[3]	values[1]	4	1			T183	1		T323	1		T324	2
auto[1]	values[3]	values[2]	13	1			T63	4		T65	1		T277	2
auto[1]	values[3]	values[3]	1	1			T223	1		-	-		-	-
auto[1]	values[3]	values[4]	11	1			T183	1		T114	1		T209	2
auto[1]	values[3]	values[5]	17	1			T188	1		T312	1		T164	2
auto[1]	values[3]	values[6]	12	1			T64	1		T211	1		T294	1
auto[1]	values[3]	values[7]	10	1			T223	2		T317	5		T314	1
auto[1]	values[4]	values[0]	8	1			T37	2		T240	1		T316	3
auto[1]	values[4]	values[1]	11	1			T249	2		T233	1		T325	4
auto[1]	values[4]	values[2]	6	1			T187	1		T183	1		T237	2
auto[1]	values[4]	values[3]	15	1			T250	2		T326	2		T327	2
auto[1]	values[4]	values[4]	11	1			T65	3		T188	1		T227	1
auto[1]	values[4]	values[5]	9	1			T177	1		T312	1		T273	1
auto[1]	values[4]	values[6]	7	1			T187	2		T223	1		T225	1
auto[1]	values[4]	values[7]	5	1			T188	1		T177	1		T313	1
auto[1]	values[5]	values[0]	24	1			T233	1		T177	2		T114	2
auto[1]	values[5]	values[1]	14	1			T41	1		T326	2		T328	3
auto[1]	values[5]	values[2]	8	1			T329	3		T330	1		T331	3
auto[1]	values[5]	values[3]	4	1			T277	1		T228	2		T76	1
auto[1]	values[5]	values[4]	16	1			T227	2		T225	1		T233	1
auto[1]	values[5]	values[5]	12	1			T80	1		T40	3		T209	1
auto[1]	values[5]	values[6]	5	1			T237	2		T316	2		T332	1
auto[1]	values[5]	values[7]	12	1			T154	1		T277	1		T333	2
auto[1]	values[6]	values[0]	8	1			T47	1		T208	1		T240	1
auto[1]	values[6]	values[1]	6	1			T154	2		T334	2		T311	1
auto[1]	values[6]	values[2]	9	1			T250	1		T314	3		T335	1
auto[1]	values[6]	values[3]	18	1			T154	1		T336	4		T337	3
auto[1]	values[6]	values[4]	12	1			T40	1		T245	1		T42	1
auto[1]	values[6]	values[5]	22	1			T185	5		T188	2		T40	3
auto[1]	values[6]	values[6]	8	1			T67	1		T216	1		T338	1
auto[1]	values[6]	values[7]	3	1			T67	2		T339	1		-	-
auto[1]	values[7]	values[0]	11	1			T37	4		T67	2		T209	3
auto[1]	values[7]	values[1]	10	1			T154	2		T177	1		T234	2
auto[1]	values[7]	values[2]	23	1			T16	4		T277	4		T340	3
auto[1]	values[7]	values[3]	12	1			T233	1		T251	1		T295	2
auto[1]	values[7]	values[4]	12	1			T67	2		T240	2		T210	2
auto[1]	values[7]	values[5]	6	1			T233	3		T237	3		-	-
auto[1]	values[7]	values[6]	7	1			T335	1		T341	1		T332	5
auto[1]	values[7]	values[7]	10	1			T56	1		T235	2		T42	4