Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	867	1			T24	21		T37	11		T38	7
all_values[1]	867	1			T24	21		T37	11		T38	7
all_values[2]	867	1			T24	21		T37	11		T38	7
all_values[3]	867	1			T24	21		T37	11		T38	7
all_values[4]	867	1			T24	21		T37	11		T38	7
all_values[5]	867	1			T24	21		T37	11		T38	7
all_values[6]	867	1			T24	21		T37	11		T38	7
all_values[7]	867	1			T24	21		T37	11		T38	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3631

1

T24

94

T37

41

T38

26

auto[1]

3305

1

T24

74

T37

47

T38

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2735

1

T24

74

T37

42

T38

27

auto[1]

4201

1

T24

94

T37

46

T38

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3949

1

T24

97

T37

55

T38

35

auto[1]

2987

1

T24

71

T37

33

T38

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T24	2		T37	2		T38	1
all_values[0]	auto[0]	auto[0]	auto[1]	92	1			T24	2		T38	1		T39	2
all_values[0]	auto[0]	auto[1]	auto[0]	164	1			T24	3		T37	4		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T24	2		T37	2		T38	2
all_values[0]	auto[1]	auto[0]	auto[1]	210	1			T24	8		T38	2		T39	5
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T24	4		T37	3		T38	1
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T24	3		T37	2		T39	1
all_values[1]	auto[0]	auto[0]	auto[1]	99	1			T24	2		T38	1		T39	1
all_values[1]	auto[0]	auto[1]	auto[0]	144	1			T24	6		T37	6		T38	3
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T24	3		T37	1		T39	1
all_values[1]	auto[1]	auto[0]	auto[1]	200	1			T24	5		T38	2		T39	5
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T24	2		T37	2		T38	1
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T24	5		T37	1		T38	3
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T24	2		T96	3		T156	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T24	6		T37	2		T38	3
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T24	1		T37	3		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T24	6		T37	2		T39	4
all_values[2]	auto[1]	auto[1]	auto[1]	191	1			T24	1		T37	3		T38	1
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T24	5		T37	5		T38	4
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T24	1		T37	1		T39	1
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T24	5		T37	3		T38	1
all_values[3]	auto[0]	auto[1]	auto[1]	97	1			T39	3		T96	1		T156	1
all_values[3]	auto[1]	auto[0]	auto[1]	205	1			T24	5		T37	2		T38	2
all_values[3]	auto[1]	auto[1]	auto[1]	169	1			T24	5		T39	3		T96	7
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T24	3		T37	1		T39	1
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T24	2		T37	2		T38	1
all_values[4]	auto[0]	auto[1]	auto[0]	147	1			T24	4		T38	3		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T24	4		T37	1		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	207	1			T24	3		T37	4		T38	1
all_values[4]	auto[1]	auto[1]	auto[1]	173	1			T24	5		T37	3		T39	2
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T24	9		T37	1		T38	1
all_values[5]	auto[0]	auto[1]	auto[0]	243	1			T24	3		T37	3		T38	3
all_values[5]	auto[1]	auto[0]	auto[1]	214	1			T24	5		T37	6		T38	2
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T24	4		T37	1		T38	1
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T24	6		T37	4		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T24	2		T37	2		T38	1
all_values[6]	auto[0]	auto[1]	auto[0]	144	1			T24	3		T38	2		T39	1
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T24	1		T37	1		T39	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T24	3		T37	3		T38	3
all_values[6]	auto[1]	auto[1]	auto[1]	186	1			T24	6		T37	1		T39	1
all_values[7]	auto[0]	auto[0]	auto[0]	184	1			T24	7		T37	3		T39	3
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T96	1		T156	1		T175	1
all_values[7]	auto[0]	auto[1]	auto[0]	155	1			T24	4		T37	5		T38	2
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T24	1		T176	4		T183	1
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T24	8		T39	4		T96	2
all_values[7]	auto[1]	auto[1]	auto[1]	200	1			T24	1		T37	3		T38	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal