Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1772

1

T12

3

T17

3

T28

3

auto[1]

1772

1

T12

7

T17

4

T28

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1874

1

T28

8

T34

5

T44

22

auto[1]

1670

1

T12

10

T17

7

T29

31

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2818

1

T12

10

T17

7

T28

3

auto[1]

726

1

T28

5

T34

3

T44

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	696	1			T12	2		T28	2		T29	8
valid[1]	731	1			T12	5		T17	3		T28	2
valid[2]	717	1			T17	2		T28	1		T29	4
valid[3]	715	1			T12	2		T28	1		T29	6
valid[4]	685	1			T12	1		T17	2		T28	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	131	1			T44	3		T69	4		T38	6
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T12	1		T29	3		T31	1
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T44	3		T69	2		T70	1
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T17	2		T29	2		T31	4
auto[0]	auto[0]	valid[2]	auto[0]	114	1			T34	1		T44	1		T69	2
auto[0]	auto[0]	valid[2]	auto[1]	169	1			T17	1		T29	1		T33	4
auto[0]	auto[0]	valid[3]	auto[0]	125	1			T69	1		T37	1		T372	1
auto[0]	auto[0]	valid[3]	auto[1]	159	1			T12	2		T29	3		T31	2
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T44	4		T69	1		T38	1
auto[0]	auto[0]	valid[4]	auto[1]	151	1			T29	2		T31	2		T33	1
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T44	1		T69	1		T97	1
auto[0]	auto[1]	valid[0]	auto[1]	157	1			T12	1		T29	5		T33	2
auto[0]	auto[1]	valid[1]	auto[0]	101	1			T44	3		T38	1		T89	1
auto[0]	auto[1]	valid[1]	auto[1]	183	1			T12	5		T17	1		T29	4
auto[0]	auto[1]	valid[2]	auto[0]	106	1			T28	1		T34	1		T69	2
auto[0]	auto[1]	valid[2]	auto[1]	175	1			T17	1		T29	3		T31	1
auto[0]	auto[1]	valid[3]	auto[0]	114	1			T28	1		T44	2		T69	1
auto[0]	auto[1]	valid[3]	auto[1]	194	1			T29	3		T31	2		T33	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T28	1		T44	1		T69	4
auto[0]	auto[1]	valid[4]	auto[1]	163	1			T12	1		T17	2		T29	5
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T28	1		T34	1		T103	1
auto[1]	auto[0]	valid[1]	auto[0]	77	1			T28	1		T69	1		T38	1
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T69	1		T64	1		T103	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T44	2		T69	1		T39	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T28	1		T372	1		T38	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T28	1		T69	3		T353	1
auto[1]	auto[1]	valid[1]	auto[0]	82	1			T28	1		T34	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T34	1		T103	1		T89	2
auto[1]	auto[1]	valid[3]	auto[0]	51	1			T103	1		T353	2		T350	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T44	1		T37	1		T38	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal