Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46980

1

T5

6

T15

5

T28

147

auto[1]

16657

1

T12

10

T17

91

T29

360

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46045

1

T5

3

T12

10

T15

4

auto[1]

17592

1

T5

3

T15

1

T28

48

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32851	1			T12	10		T15	2		T17	47
others[1]	5386	1			T5	1		T15	2		T17	10
others[2]	5345	1			T5	2		T15	1		T17	10
others[3]	6068	1			T17	4		T28	16		T29	40
interest[1]	3562	1			T17	5		T28	4		T29	14
interest[4]	21679	1			T12	10		T15	2		T17	33
interest[64]	10425	1			T5	3		T17	15		T28	22

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14898	1			T15	2		T28	52		T32	4
auto[0]	auto[0]	others[1]	2488	1			T5	1		T15	1		T28	9
auto[0]	auto[0]	others[2]	2506	1			T5	1		T15	1		T28	7
auto[0]	auto[0]	others[3]	2913	1			T28	11		T34	16		T44	31
auto[0]	auto[0]	interest[1]	1677	1			T28	2		T34	11		T44	14
auto[0]	auto[0]	interest[4]	9752	1			T15	2		T28	36		T32	2
auto[0]	auto[0]	interest[64]	4906	1			T5	1		T28	18		T32	2
auto[0]	auto[1]	others[0]	8811	1			T12	10		T17	47		T29	189
auto[0]	auto[1]	others[1]	1362	1			T17	10		T29	36		T33	18
auto[0]	auto[1]	others[2]	1418	1			T17	10		T29	24		T33	34
auto[0]	auto[1]	others[3]	1515	1			T17	4		T29	40		T33	17
auto[0]	auto[1]	interest[1]	896	1			T17	5		T29	14		T33	18
auto[0]	auto[1]	interest[4]	5907	1			T12	10		T17	33		T29	125
auto[0]	auto[1]	interest[64]	2655	1			T17	15		T29	57		T33	34
auto[1]	auto[0]	others[0]	9142	1			T28	28		T32	6		T34	60
auto[1]	auto[0]	others[1]	1536	1			T15	1		T28	4		T32	1
auto[1]	auto[0]	others[2]	1421	1			T5	1		T28	5		T34	3
auto[1]	auto[0]	others[3]	1640	1			T28	5		T34	8		T44	5
auto[1]	auto[0]	interest[1]	989	1			T28	2		T34	4		T44	7
auto[1]	auto[0]	interest[4]	6020	1			T28	17		T32	5		T34	38
auto[1]	auto[0]	interest[64]	2864	1			T5	2		T28	4		T34	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal