Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2866173	1			T1	1		T3	1		T4	1
all_values[1]	2866173	1			T1	1		T3	1		T4	1
all_values[2]	2866173	1			T1	1		T3	1		T4	1
all_values[3]	2866173	1			T1	1		T3	1		T4	1
all_values[4]	2866173	1			T1	1		T3	1		T4	1
all_values[5]	2866173	1			T1	1		T3	1		T4	1
all_values[6]	2866173	1			T1	1		T3	1		T4	1
all_values[7]	2866173	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946988

1

T1

8

T3

8

T4

8

auto[1]

982396

1

T32

115

T35

101

T95

2883

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22901385

1

T1

8

T3

8

T4

8

auto[1]

27999

1

T58

39

T32

80

T48

139

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2761881	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	12653	1			T58	39		T32	2		T48	66
all_values[0]	auto[1]	auto[0]	90666	1			T32	18		T35	5		T95	549
all_values[0]	auto[1]	auto[1]	973	1			T32	3		T35	7		T95	27
all_values[1]	auto[0]	auto[0]	2672267	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	8287	1			T32	6		T48	66		T49	40
all_values[1]	auto[1]	auto[0]	184907	1			T32	6		T35	7		T95	546
all_values[1]	auto[1]	auto[1]	712	1			T32	5		T35	4		T95	30
all_values[2]	auto[0]	auto[0]	2745866	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2862	1			T32	6		T48	7		T45	10
all_values[2]	auto[1]	auto[0]	116968	1			T32	3		T35	8		T95	546
all_values[2]	auto[1]	auto[1]	477	1			T32	5		T35	8		T95	30
all_values[3]	auto[0]	auto[0]	2797171	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	206	1			T32	5		T35	9		T95	3
all_values[3]	auto[1]	auto[0]	68589	1			T32	10		T35	3		T95	1
all_values[3]	auto[1]	auto[1]	207	1			T32	7		T35	8		T36	6
all_values[4]	auto[0]	auto[0]	2788732	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	192	1			T32	2		T35	7		T36	3
all_values[4]	auto[1]	auto[0]	77047	1			T32	18		T35	10		T95	574
all_values[4]	auto[1]	auto[1]	202	1			T32	3		T35	5		T95	2
all_values[5]	auto[0]	auto[0]	2772898	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	198	1			T32	2		T35	8		T95	2
all_values[5]	auto[1]	auto[0]	92878	1			T32	10		T35	4		T36	5
all_values[5]	auto[1]	auto[1]	199	1			T32	7		T35	4		T36	5
all_values[6]	auto[0]	auto[0]	2675940	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	225	1			T32	12		T35	8		T36	5
all_values[6]	auto[1]	auto[0]	189823	1			T32	1		T35	12		T95	2
all_values[6]	auto[1]	auto[1]	185	1			T32	7		T35	1		T36	3
all_values[7]	auto[0]	auto[0]	2707372	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	238	1			T32	5		T35	8		T36	5
all_values[7]	auto[1]	auto[0]	158380	1			T32	9		T35	6		T95	576
all_values[7]	auto[1]	auto[1]	183	1			T32	3		T35	9		T36	6