Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.11 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.59 62.59 92.45 92.45 78.45 78.45 61.61 61.61 31.11 31.11 88.92 88.92 71.86 71.86 13.71 13.71 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3288465677
73.95 11.37 95.23 2.78 83.73 5.28 63.29 1.67 73.33 42.22 92.59 3.67 78.86 7.00 30.64 16.93 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2981059134
80.07 6.11 96.87 1.64 87.23 3.49 87.50 24.21 77.78 4.44 94.82 2.23 84.29 5.43 31.98 1.34 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.1072077743
83.99 3.92 97.14 0.27 87.88 0.66 87.50 0.00 88.89 11.11 95.28 0.46 84.43 0.14 46.78 14.80 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.590743449
86.38 2.40 97.53 0.39 88.77 0.88 88.09 0.59 88.89 0.00 95.70 0.42 84.57 0.14 61.14 14.36 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3474766155
87.96 1.57 97.55 0.02 88.92 0.15 88.68 0.59 88.89 0.00 95.74 0.03 93.00 8.43 62.92 1.78 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.1246387888
89.49 1.53 97.63 0.08 89.16 0.25 88.68 0.00 91.11 2.22 95.86 0.12 93.14 0.14 70.84 7.92 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3618519321
90.29 0.80 97.63 0.00 89.28 0.11 90.35 1.67 91.11 0.00 95.86 0.00 93.43 0.29 74.36 3.51 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.192233567
90.97 0.68 97.64 0.01 89.30 0.02 95.08 4.72 91.11 0.00 95.89 0.03 93.43 0.00 74.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2190816095
91.58 0.61 98.00 0.36 92.05 2.75 95.08 0.00 91.11 0.00 96.46 0.58 94.00 0.57 74.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3702329433
92.18 0.60 98.00 0.00 92.10 0.05 95.08 0.00 93.33 2.22 96.48 0.02 94.00 0.00 76.29 1.93 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3914408059
92.74 0.56 98.03 0.03 92.13 0.04 95.08 0.00 93.33 0.00 96.55 0.07 94.00 0.00 80.05 3.76 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2970066625
93.16 0.42 98.03 0.00 92.16 0.02 97.64 2.56 93.33 0.00 96.55 0.00 94.14 0.14 80.30 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3333920319
93.58 0.42 98.03 0.00 92.16 0.00 97.64 0.00 93.33 0.00 96.55 0.00 94.14 0.00 83.22 2.92 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1896957289
93.93 0.35 98.03 0.00 92.93 0.77 98.03 0.39 93.33 0.00 96.58 0.03 94.43 0.29 84.16 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.954858664
94.23 0.30 98.03 0.00 92.93 0.00 98.03 0.00 93.33 0.00 96.58 0.00 94.43 0.00 86.29 2.13 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3001522271
94.52 0.29 98.14 0.11 93.25 0.32 98.03 0.00 93.33 0.00 96.79 0.20 94.43 0.00 87.67 1.39 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1438896704
94.77 0.25 98.14 0.00 93.25 0.00 98.03 0.00 93.33 0.00 96.79 0.00 94.43 0.00 89.41 1.73 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.476623008
94.97 0.20 98.31 0.17 93.59 0.34 98.03 0.00 93.33 0.00 97.09 0.30 94.43 0.00 90.00 0.59 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3865593274
95.16 0.19 98.31 0.00 93.59 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.43 0.00 91.34 1.34 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.319643738
95.33 0.17 98.31 0.00 93.59 0.00 98.03 0.00 93.33 0.00 97.09 0.00 94.43 0.00 92.52 1.19 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2938154266
95.47 0.14 98.31 0.00 93.59 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.43 1.00 92.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3398540193
95.61 0.14 98.34 0.03 93.61 0.02 98.03 0.00 93.33 0.00 97.14 0.05 95.43 0.00 93.42 0.89 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.546985465
95.71 0.10 98.34 0.00 93.61 0.00 98.03 0.00 93.33 0.00 97.14 0.00 95.43 0.00 94.11 0.69 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2495152325
95.81 0.09 98.39 0.06 93.72 0.11 98.43 0.39 93.33 0.00 97.23 0.08 95.43 0.00 94.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.509326296
95.88 0.08 98.39 0.00 93.72 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 94.65 0.54 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3267041041
95.96 0.07 98.39 0.00 93.79 0.06 98.43 0.00 93.33 0.00 97.28 0.05 95.43 0.00 95.05 0.40 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1172429080
96.03 0.07 98.39 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.28 0.00 95.43 0.00 95.54 0.50 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3261187785
96.08 0.06 98.39 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.28 0.00 95.43 0.00 95.94 0.40 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.3483813560
96.13 0.04 98.39 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.28 0.00 95.43 0.00 96.24 0.30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.429150338
96.17 0.04 98.39 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.28 0.00 95.43 0.00 96.53 0.30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2538223424
96.21 0.04 98.39 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.28 0.00 95.43 0.00 96.83 0.30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.4223742187
96.25 0.04 98.42 0.03 93.82 0.04 98.62 0.20 93.33 0.00 97.28 0.00 95.43 0.00 96.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.668059893
96.29 0.04 98.42 0.00 93.84 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.08 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1426634844
96.32 0.04 98.42 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.33 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.3938528196
96.36 0.04 98.42 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.57 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.125751904
96.38 0.03 98.42 0.00 93.99 0.15 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.62 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.731980547
96.41 0.03 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 97.82 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3801464413
96.44 0.03 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.02 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1182914445
96.46 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2642835073
96.48 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.34430606
96.49 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.147847258
96.50 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1120537791
96.52 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.4266834797
96.53 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.4197045621
96.55 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1817794797
96.56 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3364537076
96.58 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.96 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3135863201
96.58 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4002158039
96.59 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.129934490
96.60 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2073296301
96.60 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.4225293988
96.61 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3934665641
96.62 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3397256344
96.62 0.01 98.44 0.02 94.01 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2254999411
96.63 0.01 98.44 0.00 94.04 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2199945959
96.63 0.01 98.44 0.00 94.06 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1962410147
96.63 0.01 98.44 0.00 94.08 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1083346664
96.64 0.01 98.44 0.00 94.10 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3301618903
96.64 0.01 98.44 0.00 94.11 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.539939862

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2587524493
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.645575445
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.312520774
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4287636390
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2509465799
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3828065920
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2369997803
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2950654372
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3881608798
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.153466447
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.287526141
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3431461167
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.697313809
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1634626595
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.385421723
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3768292515
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1540430717
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.575773155
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.652674986
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2922647740
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3510438536
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2719555926
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2446805667
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1016621696
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3741667977
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1971416137
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/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3372089102
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2079412883
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3337974914
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.958956305
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2950534740
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3662031516
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2448173823
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.318172485
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.534619482
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.533430806
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1349271855
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3398692087
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1978416902
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2744155484
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3528622167
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3962725149
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3656639170
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2973117285
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3490377913
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3650661026
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.1618454409
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.422616227
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.2984015832
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1400754847
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2532400763
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2934748434
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1289370542
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.177942351
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2864176588
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2571599915
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.607665931
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2257922281
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3503085838
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.445810833
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.4099457856
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.792659819
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2643293292
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3613937355
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1026700212
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4110067445
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2049162568
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.406250780
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.405483509
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.491235997
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1979817857
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2350628227
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1752351115
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.640698126
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1720377285
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2331972598
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2049610199
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2018823366
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2592290074
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2041140324
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3087961509
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1887741762
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.239993686
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1913754929
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1520076951
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2095175897
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.621555049
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2130600696
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.321373927
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1587749427



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2254999411 Aug 25 10:56:25 AM UTC 24 Aug 25 10:56:28 AM UTC 24 19703084 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.509326296 Aug 25 10:56:26 AM UTC 24 Aug 25 10:56:29 AM UTC 24 87571989 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2190816095 Aug 25 10:56:27 AM UTC 24 Aug 25 10:56:30 AM UTC 24 15261463 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2273520880 Aug 25 10:56:29 AM UTC 24 Aug 25 10:56:32 AM UTC 24 223687171 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.116538462 Aug 25 10:56:27 AM UTC 24 Aug 25 10:56:32 AM UTC 24 910927201 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.1072077743 Aug 25 10:56:29 AM UTC 24 Aug 25 10:56:33 AM UTC 24 305170588 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1198062594 Aug 25 10:56:27 AM UTC 24 Aug 25 10:56:41 AM UTC 24 1307851165 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3224695511 Aug 25 10:56:31 AM UTC 24 Aug 25 10:56:43 AM UTC 24 1403450243 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3151577492 Aug 25 10:56:33 AM UTC 24 Aug 25 10:56:46 AM UTC 24 1041585109 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3288465677 Aug 25 10:56:30 AM UTC 24 Aug 25 10:56:46 AM UTC 24 8965611488 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1438896704 Aug 25 10:56:33 AM UTC 24 Aug 25 10:56:49 AM UTC 24 374429852 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3256069414 Aug 25 10:56:30 AM UTC 24 Aug 25 10:56:50 AM UTC 24 3792369396 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3333920319 Aug 25 10:56:42 AM UTC 24 Aug 25 10:56:51 AM UTC 24 83340201 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.668059893 Aug 25 10:56:44 AM UTC 24 Aug 25 10:56:51 AM UTC 24 31227839 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.538353533 Aug 25 10:56:45 AM UTC 24 Aug 25 10:56:51 AM UTC 24 131173948 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1065397457 Aug 25 10:56:47 AM UTC 24 Aug 25 10:56:52 AM UTC 24 10615732 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.243695772 Aug 25 10:56:49 AM UTC 24 Aug 25 10:56:53 AM UTC 24 33739038 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3909586441 Aug 25 10:56:47 AM UTC 24 Aug 25 10:56:53 AM UTC 24 33496290 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1166492525 Aug 25 10:56:50 AM UTC 24 Aug 25 10:56:53 AM UTC 24 21591310 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1083346664 Aug 25 10:56:52 AM UTC 24 Aug 25 10:56:57 AM UTC 24 580661819 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.713785669 Aug 25 10:56:52 AM UTC 24 Aug 25 10:56:57 AM UTC 24 117309533 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.430502349 Aug 25 10:56:51 AM UTC 24 Aug 25 10:56:58 AM UTC 24 1368353374 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.34430606 Aug 25 10:56:52 AM UTC 24 Aug 25 10:56:59 AM UTC 24 1072253578 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3322743181 Aug 25 10:56:52 AM UTC 24 Aug 25 10:56:59 AM UTC 24 340516676 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.2807878730 Aug 25 10:56:58 AM UTC 24 Aug 25 10:57:00 AM UTC 24 25217561 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.930557729 Aug 25 10:56:58 AM UTC 24 Aug 25 10:57:01 AM UTC 24 561288037 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.3145141380 Aug 25 10:56:59 AM UTC 24 Aug 25 10:57:01 AM UTC 24 54268261 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.325113698 Aug 25 10:56:59 AM UTC 24 Aug 25 10:57:02 AM UTC 24 108653497 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2946813881 Aug 25 10:57:01 AM UTC 24 Aug 25 10:57:04 AM UTC 24 60702144 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1172429080 Aug 25 10:56:32 AM UTC 24 Aug 25 10:57:04 AM UTC 24 3631894537 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.841952714 Aug 25 10:56:52 AM UTC 24 Aug 25 10:57:05 AM UTC 24 4947631195 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.273422241 Aug 25 10:57:02 AM UTC 24 Aug 25 10:57:06 AM UTC 24 114167456 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3127975769 Aug 25 10:56:53 AM UTC 24 Aug 25 10:57:07 AM UTC 24 1854237185 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1406984601 Aug 25 10:57:02 AM UTC 24 Aug 25 10:57:08 AM UTC 24 1518358361 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3702329433 Aug 25 10:56:33 AM UTC 24 Aug 25 10:57:09 AM UTC 24 1740352659 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.2072090643 Aug 25 10:57:06 AM UTC 24 Aug 25 10:57:10 AM UTC 24 421433319 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.348215834 Aug 25 10:57:07 AM UTC 24 Aug 25 10:57:11 AM UTC 24 413125040 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3675672176 Aug 25 10:57:02 AM UTC 24 Aug 25 10:57:13 AM UTC 24 1275984137 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.3946894965 Aug 25 10:57:08 AM UTC 24 Aug 25 10:57:15 AM UTC 24 233704113 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.1618358144 Aug 25 10:56:52 AM UTC 24 Aug 25 10:57:18 AM UTC 24 1055183271 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3662260903 Aug 25 10:56:30 AM UTC 24 Aug 25 10:57:18 AM UTC 24 13124446256 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.435400888 Aug 25 10:57:16 AM UTC 24 Aug 25 10:57:19 AM UTC 24 78841063 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2085727752 Aug 25 10:57:05 AM UTC 24 Aug 25 10:57:20 AM UTC 24 20695986498 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1268660945 Aug 25 10:57:18 AM UTC 24 Aug 25 10:57:21 AM UTC 24 13472013 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.147847258 Aug 25 10:56:53 AM UTC 24 Aug 25 10:57:21 AM UTC 24 1264291954 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.199847410 Aug 25 10:57:19 AM UTC 24 Aug 25 10:57:21 AM UTC 24 50930200 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2647142926 Aug 25 10:57:10 AM UTC 24 Aug 25 10:57:23 AM UTC 24 6994744262 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.102018433 Aug 25 10:57:26 AM UTC 24 Aug 25 10:57:56 AM UTC 24 2122512462 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1980681676 Aug 25 10:56:49 AM UTC 24 Aug 25 10:57:23 AM UTC 24 5409279340 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.1767395736 Aug 25 10:57:21 AM UTC 24 Aug 25 10:57:24 AM UTC 24 25947314 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2003566675 Aug 25 10:57:22 AM UTC 24 Aug 25 10:57:24 AM UTC 24 65753156 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3865593274 Aug 25 10:57:00 AM UTC 24 Aug 25 10:57:25 AM UTC 24 10703983620 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.778633608 Aug 25 10:57:22 AM UTC 24 Aug 25 10:57:25 AM UTC 24 235915896 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.782745188 Aug 25 10:57:07 AM UTC 24 Aug 25 10:57:31 AM UTC 24 4375261677 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4068734619 Aug 25 10:57:24 AM UTC 24 Aug 25 10:57:33 AM UTC 24 2559403062 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3423553609 Aug 25 10:57:22 AM UTC 24 Aug 25 10:57:36 AM UTC 24 1173116872 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.400220345 Aug 25 10:57:25 AM UTC 24 Aug 25 10:57:36 AM UTC 24 360000363 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2981059134 Aug 25 10:56:40 AM UTC 24 Aug 25 10:57:41 AM UTC 24 2107471134 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2892732913 Aug 25 10:57:32 AM UTC 24 Aug 25 10:57:41 AM UTC 24 146047761 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4238645468 Aug 25 10:57:36 AM UTC 24 Aug 25 10:57:42 AM UTC 24 359778620 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2854306331 Aug 25 10:57:00 AM UTC 24 Aug 25 10:57:44 AM UTC 24 5318597252 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.3190228086 Aug 25 10:57:42 AM UTC 24 Aug 25 10:57:44 AM UTC 24 14816368 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2477734162 Aug 25 10:57:42 AM UTC 24 Aug 25 10:57:45 AM UTC 24 747094909 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.503734742 Aug 25 10:57:43 AM UTC 24 Aug 25 10:57:46 AM UTC 24 23682013 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1424081176 Aug 25 10:57:44 AM UTC 24 Aug 25 10:57:47 AM UTC 24 179620324 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2263254053 Aug 25 10:57:46 AM UTC 24 Aug 25 10:57:54 AM UTC 24 461797020 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.2680446095 Aug 25 10:57:47 AM UTC 24 Aug 25 10:57:55 AM UTC 24 158598528 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1522617858 Aug 25 10:57:45 AM UTC 24 Aug 25 10:57:57 AM UTC 24 1884039223 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3292355546 Aug 25 10:57:25 AM UTC 24 Aug 25 10:57:59 AM UTC 24 3403906930 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1172608982 Aug 25 10:56:31 AM UTC 24 Aug 25 10:58:01 AM UTC 24 8167374001 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3718715575 Aug 25 10:57:50 AM UTC 24 Aug 25 10:58:04 AM UTC 24 1388698693 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.3384177257 Aug 25 10:57:53 AM UTC 24 Aug 25 10:58:04 AM UTC 24 855182193 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.3869097008 Aug 25 10:57:46 AM UTC 24 Aug 25 10:58:04 AM UTC 24 12738944810 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.492923605 Aug 25 10:57:56 AM UTC 24 Aug 25 10:58:04 AM UTC 24 282192305 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3344687458 Aug 25 10:58:02 AM UTC 24 Aug 25 10:58:05 AM UTC 24 68602591 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3762117221 Aug 25 10:58:04 AM UTC 24 Aug 25 10:58:07 AM UTC 24 59819007 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.796640530 Aug 25 10:58:05 AM UTC 24 Aug 25 10:58:07 AM UTC 24 14167918 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1728316772 Aug 25 10:58:05 AM UTC 24 Aug 25 10:58:07 AM UTC 24 40948437 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.2471347597 Aug 25 10:58:05 AM UTC 24 Aug 25 10:58:08 AM UTC 24 50774876 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.3389584572 Aug 25 10:58:06 AM UTC 24 Aug 25 10:58:08 AM UTC 24 25088821 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4047419411 Aug 25 10:58:07 AM UTC 24 Aug 25 10:58:10 AM UTC 24 41772433 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.3166424580 Aug 25 10:57:26 AM UTC 24 Aug 25 10:58:11 AM UTC 24 13936948108 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.4111255788 Aug 25 10:58:08 AM UTC 24 Aug 25 10:58:12 AM UTC 24 23991570 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.4212597019 Aug 25 10:57:21 AM UTC 24 Aug 25 10:58:12 AM UTC 24 9513473549 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1671133612 Aug 25 10:57:55 AM UTC 24 Aug 25 10:58:13 AM UTC 24 8943876182 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3718699095 Aug 25 10:57:48 AM UTC 24 Aug 25 10:58:14 AM UTC 24 14540836643 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3081380082 Aug 25 10:58:01 AM UTC 24 Aug 25 10:58:15 AM UTC 24 275703845 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2773863331 Aug 25 10:57:57 AM UTC 24 Aug 25 10:58:15 AM UTC 24 1586046166 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2588388841 Aug 25 10:58:08 AM UTC 24 Aug 25 10:58:16 AM UTC 24 470272470 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.569716474 Aug 25 10:58:10 AM UTC 24 Aug 25 10:58:17 AM UTC 24 195311752 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3548851582 Aug 25 10:58:09 AM UTC 24 Aug 25 10:58:19 AM UTC 24 22554605388 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1411741413 Aug 25 10:58:05 AM UTC 24 Aug 25 10:58:20 AM UTC 24 7231124823 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3336667552 Aug 25 10:57:23 AM UTC 24 Aug 25 10:58:21 AM UTC 24 10595659798 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.3193949509 Aug 25 10:58:12 AM UTC 24 Aug 25 10:58:22 AM UTC 24 1252398061 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3489443940 Aug 25 10:58:14 AM UTC 24 Aug 25 10:58:22 AM UTC 24 2276268615 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1496884242 Aug 25 10:58:20 AM UTC 24 Aug 25 10:58:23 AM UTC 24 27973350 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1410935508 Aug 25 10:58:21 AM UTC 24 Aug 25 10:58:23 AM UTC 24 16229875 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.590743449 Aug 25 10:56:39 AM UTC 24 Aug 25 10:58:23 AM UTC 24 5704432450 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3946430029 Aug 25 10:58:21 AM UTC 24 Aug 25 10:58:23 AM UTC 24 31789269 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.446549969 Aug 25 10:57:56 AM UTC 24 Aug 25 10:58:24 AM UTC 24 2809150836 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.958956305 Aug 25 10:58:23 AM UTC 24 Aug 25 10:58:25 AM UTC 24 66594135 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3618519321 Aug 25 10:56:34 AM UTC 24 Aug 25 10:58:26 AM UTC 24 5286488648 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3337974914 Aug 25 10:58:24 AM UTC 24 Aug 25 10:58:27 AM UTC 24 36857529 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4188213350 Aug 25 10:58:24 AM UTC 24 Aug 25 10:58:29 AM UTC 24 178263348 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1791932151 Aug 25 10:58:24 AM UTC 24 Aug 25 10:58:29 AM UTC 24 293176982 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2366168029 Aug 25 10:58:13 AM UTC 24 Aug 25 10:58:30 AM UTC 24 5287708777 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3372089102 Aug 25 10:58:23 AM UTC 24 Aug 25 10:58:33 AM UTC 24 1715710741 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.812250665 Aug 25 10:58:26 AM UTC 24 Aug 25 10:58:34 AM UTC 24 766089972 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2541580605 Aug 25 10:58:24 AM UTC 24 Aug 25 10:58:34 AM UTC 24 3047705232 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.173813639 Aug 25 10:58:26 AM UTC 24 Aug 25 10:58:35 AM UTC 24 133572105 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2950534740 Aug 25 10:58:25 AM UTC 24 Aug 25 10:58:36 AM UTC 24 1546389344 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.4100191020 Aug 25 10:57:11 AM UTC 24 Aug 25 10:58:36 AM UTC 24 4921917631 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.3335583613 Aug 25 10:58:35 AM UTC 24 Aug 25 10:58:38 AM UTC 24 51319425 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3298073164 Aug 25 10:58:14 AM UTC 24 Aug 25 10:58:38 AM UTC 24 646801914 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.3373304865 Aug 25 10:58:35 AM UTC 24 Aug 25 10:58:39 AM UTC 24 143291990 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.318172485 Aug 25 10:58:36 AM UTC 24 Aug 25 10:58:39 AM UTC 24 110752229 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2079412883 Aug 25 10:58:22 AM UTC 24 Aug 25 10:58:39 AM UTC 24 2858326956 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3962725149 Aug 25 10:58:37 AM UTC 24 Aug 25 10:58:41 AM UTC 24 217611985 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1400754847 Aug 25 10:58:39 AM UTC 24 Aug 25 10:58:42 AM UTC 24 19640513 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.2085871151 Aug 25 10:57:54 AM UTC 24 Aug 25 10:58:43 AM UTC 24 17266085450 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1595909421 Aug 25 10:57:37 AM UTC 24 Aug 25 10:58:43 AM UTC 24 5142009721 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3656639170 Aug 25 10:58:41 AM UTC 24 Aug 25 10:58:45 AM UTC 24 31312038 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.2984015832 Aug 25 10:58:39 AM UTC 24 Aug 25 10:58:46 AM UTC 24 230520679 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.2869473854 Aug 25 10:57:59 AM UTC 24 Aug 25 10:58:46 AM UTC 24 47194366856 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2973117285 Aug 25 10:58:41 AM UTC 24 Aug 25 10:58:46 AM UTC 24 1168306625 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3001522271 Aug 25 10:56:54 AM UTC 24 Aug 25 10:58:48 AM UTC 24 3646063850 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.841123294 Aug 25 10:58:25 AM UTC 24 Aug 25 10:58:48 AM UTC 24 4789202649 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1817794797 Aug 25 10:57:09 AM UTC 24 Aug 25 10:58:48 AM UTC 24 2821968309 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.422616227 Aug 25 10:58:37 AM UTC 24 Aug 25 10:58:49 AM UTC 24 1280918953 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2448173823 Aug 25 10:58:44 AM UTC 24 Aug 25 10:58:50 AM UTC 24 158113633 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3662031516 Aug 25 10:58:50 AM UTC 24 Aug 25 10:58:52 AM UTC 24 43508016 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.177942351 Aug 25 10:58:50 AM UTC 24 Aug 25 10:58:52 AM UTC 24 30164364 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.492891764 Aug 25 10:58:30 AM UTC 24 Aug 25 10:58:53 AM UTC 24 2790078811 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.4099457856 Aug 25 10:58:51 AM UTC 24 Aug 25 10:58:54 AM UTC 24 28549528 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.405483509 Aug 25 10:58:53 AM UTC 24 Aug 25 10:58:55 AM UTC 24 20067371 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.406250780 Aug 25 10:58:53 AM UTC 24 Aug 25 10:58:57 AM UTC 24 168719134 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3490377913 Aug 25 10:58:46 AM UTC 24 Aug 25 10:58:59 AM UTC 24 1708794166 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4110067445 Aug 25 10:58:51 AM UTC 24 Aug 25 10:59:00 AM UTC 24 3272989196 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2049162568 Aug 25 10:58:51 AM UTC 24 Aug 25 10:59:01 AM UTC 24 3273738462 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2643293292 Aug 25 10:58:54 AM UTC 24 Aug 25 10:59:02 AM UTC 24 383511711 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.445810833 Aug 25 10:58:58 AM UTC 24 Aug 25 10:59:04 AM UTC 24 58297733 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.491235997 Aug 25 10:59:00 AM UTC 24 Aug 25 10:59:04 AM UTC 24 1126258980 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.792659819 Aug 25 10:58:54 AM UTC 24 Aug 25 10:59:04 AM UTC 24 3452154558 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3503085838 Aug 25 10:58:56 AM UTC 24 Aug 25 10:59:04 AM UTC 24 1246690520 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.1618454409 Aug 25 10:58:39 AM UTC 24 Aug 25 10:59:05 AM UTC 24 20208972523 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1289370542 Aug 25 10:59:01 AM UTC 24 Aug 25 10:59:06 AM UTC 24 82425233 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3528622167 Aug 25 10:58:43 AM UTC 24 Aug 25 10:59:06 AM UTC 24 1764411521 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2934748434 Aug 25 10:59:05 AM UTC 24 Aug 25 10:59:08 AM UTC 24 16307902 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2532400763 Aug 25 10:58:43 AM UTC 24 Aug 25 10:59:08 AM UTC 24 8406199516 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1026700212 Aug 25 10:59:05 AM UTC 24 Aug 25 10:59:08 AM UTC 24 503848770 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1752351115 Aug 25 10:59:06 AM UTC 24 Aug 25 10:59:09 AM UTC 24 26779065 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3087961509 Aug 25 10:59:07 AM UTC 24 Aug 25 10:59:09 AM UTC 24 292232946 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2095175897 Aug 25 10:59:09 AM UTC 24 Aug 25 10:59:11 AM UTC 24 21684581 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.321373927 Aug 25 10:59:09 AM UTC 24 Aug 25 10:59:12 AM UTC 24 62009109 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3914408059 Aug 25 10:56:55 AM UTC 24 Aug 25 10:59:12 AM UTC 24 24885912478 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2130600696 Aug 25 10:59:09 AM UTC 24 Aug 25 10:59:13 AM UTC 24 77049580 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2864176588 Aug 25 10:59:04 AM UTC 24 Aug 25 10:59:13 AM UTC 24 746689173 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3613937355 Aug 25 10:59:02 AM UTC 24 Aug 25 10:59:14 AM UTC 24 1736261026 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.239993686 Aug 25 10:59:10 AM UTC 24 Aug 25 10:59:15 AM UTC 24 113066350 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.607665931 Aug 25 10:59:02 AM UTC 24 Aug 25 10:59:16 AM UTC 24 6974437053 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3398692087 Aug 25 10:58:44 AM UTC 24 Aug 25 10:59:16 AM UTC 24 9199500833 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.3691332734 Aug 25 10:58:13 AM UTC 24 Aug 25 10:59:17 AM UTC 24 16771130832 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1887741762 Aug 25 10:59:10 AM UTC 24 Aug 25 10:59:18 AM UTC 24 478204963 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2211376091 Aug 25 10:57:37 AM UTC 24 Aug 25 10:59:22 AM UTC 24 2661787174 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2744155484 Aug 25 10:58:42 AM UTC 24 Aug 25 10:59:23 AM UTC 24 13850289008 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2041140324 Aug 25 10:59:12 AM UTC 24 Aug 25 10:59:25 AM UTC 24 114339735 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3371426202 Aug 25 10:58:34 AM UTC 24 Aug 25 10:59:25 AM UTC 24 15536113273 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1979817857 Aug 25 10:59:23 AM UTC 24 Aug 25 10:59:26 AM UTC 24 13929492 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.3386595239 Aug 25 10:59:23 AM UTC 24 Aug 25 10:59:26 AM UTC 24 71450635 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.400722315 Aug 25 10:59:23 AM UTC 24 Aug 25 10:59:26 AM UTC 24 65586655 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2592290074 Aug 25 10:59:11 AM UTC 24 Aug 25 10:59:28 AM UTC 24 4451637177 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1540337981 Aug 25 10:59:26 AM UTC 24 Aug 25 10:59:28 AM UTC 24 233777876 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.4100793057 Aug 25 10:59:26 AM UTC 24 Aug 25 10:59:29 AM UTC 24 134519541 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.399792770 Aug 25 10:59:27 AM UTC 24 Aug 25 10:59:31 AM UTC 24 27853892 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2049610199 Aug 25 10:59:15 AM UTC 24 Aug 25 10:59:32 AM UTC 24 699856627 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1913754929 Aug 25 10:59:17 AM UTC 24 Aug 25 10:59:32 AM UTC 24 327390622 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.534619482 Aug 25 10:58:46 AM UTC 24 Aug 25 10:59:32 AM UTC 24 5031891092 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.640698126 Aug 25 10:59:17 AM UTC 24 Aug 25 10:59:35 AM UTC 24 678714168 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2350628227 Aug 25 10:59:13 AM UTC 24 Aug 25 10:59:35 AM UTC 24 846843136 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3050756354 Aug 25 10:59:27 AM UTC 24 Aug 25 10:59:36 AM UTC 24 432191692 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1978416902 Aug 25 10:58:45 AM UTC 24 Aug 25 10:59:37 AM UTC 24 1100549493 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.844688246 Aug 25 10:58:11 AM UTC 24 Aug 25 10:59:37 AM UTC 24 8020836871 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1156486828 Aug 25 10:59:26 AM UTC 24 Aug 25 10:59:37 AM UTC 24 936985854 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.749759553 Aug 25 10:59:26 AM UTC 24 Aug 25 10:59:38 AM UTC 24 242343256 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.3660546624 Aug 25 10:59:33 AM UTC 24 Aug 25 10:59:39 AM UTC 24 210479414 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.382877711 Aug 25 10:59:37 AM UTC 24 Aug 25 10:59:39 AM UTC 24 39624188 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2346297026 Aug 25 10:59:37 AM UTC 24 Aug 25 10:59:39 AM UTC 24 17029151 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.675920610 Aug 25 10:59:37 AM UTC 24 Aug 25 10:59:40 AM UTC 24 44418896 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.4222009002 Aug 25 10:59:38 AM UTC 24 Aug 25 10:59:40 AM UTC 24 15870528 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.799394525 Aug 25 10:59:40 AM UTC 24 Aug 25 10:59:42 AM UTC 24 87453555 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.621555049 Aug 25 10:59:07 AM UTC 24 Aug 25 10:59:42 AM UTC 24 5346814237 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1609468624 Aug 25 10:59:41 AM UTC 24 Aug 25 10:59:44 AM UTC 24 146548305 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2169332869 Aug 25 10:59:33 AM UTC 24 Aug 25 10:59:45 AM UTC 24 3805753487 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1988616142 Aug 25 10:59:30 AM UTC 24 Aug 25 10:59:46 AM UTC 24 1704547903 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2495152325 Aug 25 10:57:13 AM UTC 24 Aug 25 10:59:46 AM UTC 24 17373643024 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3650661026 Aug 25 10:58:50 AM UTC 24 Aug 25 10:59:48 AM UTC 24 5020069215 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.2910294624 Aug 25 10:59:28 AM UTC 24 Aug 25 10:59:48 AM UTC 24 1071179620 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2321651252 Aug 25 10:58:30 AM UTC 24 Aug 25 10:59:49 AM UTC 24 3377912690 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2291262535 Aug 25 10:59:48 AM UTC 24 Aug 25 10:59:50 AM UTC 24 15793554 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2423674616 Aug 25 10:59:45 AM UTC 24 Aug 25 10:59:50 AM UTC 24 127222997 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2590964369 Aug 25 10:59:42 AM UTC 24 Aug 25 10:59:50 AM UTC 24 556397531 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1587749427 Aug 25 10:59:12 AM UTC 24 Aug 25 10:59:51 AM UTC 24 7785641677 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.727000221 Aug 25 10:59:50 AM UTC 24 Aug 25 10:59:52 AM UTC 24 37547288 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.3962369031 Aug 25 10:59:50 AM UTC 24 Aug 25 10:59:52 AM UTC 24 43192004 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3430259232 Aug 25 10:59:50 AM UTC 24 Aug 25 10:59:53 AM UTC 24 35130061 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.812396664 Aug 25 10:59:39 AM UTC 24 Aug 25 10:59:54 AM UTC 24 810706521 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.955837825 Aug 25 10:59:44 AM UTC 24 Aug 25 10:59:55 AM UTC 24 3220699250 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1390531102 Aug 25 10:59:34 AM UTC 24 Aug 25 10:59:56 AM UTC 24 3680647119 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4119424526 Aug 25 10:59:54 AM UTC 24 Aug 25 10:59:56 AM UTC 24 66613990 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.2469407216 Aug 25 10:59:54 AM UTC 24 Aug 25 10:59:56 AM UTC 24 175852177 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3792502617 Aug 25 10:59:51 AM UTC 24 Aug 25 10:59:58 AM UTC 24 10987601400 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1302101479 Aug 25 10:59:41 AM UTC 24 Aug 25 10:59:58 AM UTC 24 11390488002 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3397256344 Aug 25 10:59:52 AM UTC 24 Aug 25 11:00:02 AM UTC 24 743547486 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2257922281 Aug 25 10:59:02 AM UTC 24 Aug 25 11:00:02 AM UTC 24 1849272175 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.887577566 Aug 25 10:59:25 AM UTC 24 Aug 25 11:00:03 AM UTC 24 14085682198 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3560939669 Aug 25 10:59:46 AM UTC 24 Aug 25 11:00:05 AM UTC 24 2254707178 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.2073505863 Aug 25 11:00:00 AM UTC 24 Aug 25 11:00:07 AM UTC 24 252615355 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.366098286 Aug 25 10:59:57 AM UTC 24 Aug 25 11:00:08 AM UTC 24 823376922 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.888942416 Aug 25 10:59:59 AM UTC 24 Aug 25 11:00:08 AM UTC 24 743502624 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.2161229937 Aug 25 10:59:57 AM UTC 24 Aug 25 11:00:08 AM UTC 24 1557425599 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.252731345 Aug 25 11:00:08 AM UTC 24 Aug 25 11:00:10 AM UTC 24 12562732 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3400880059 Aug 25 11:00:08 AM UTC 24 Aug 25 11:00:10 AM UTC 24 12596767 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.191467529 Aug 25 10:59:56 AM UTC 24 Aug 25 11:00:10 AM UTC 24 554026202 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.819092573 Aug 25 10:58:27 AM UTC 24 Aug 25 11:00:11 AM UTC 24 37830837467 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3485540225 Aug 25 10:59:54 AM UTC 24 Aug 25 11:00:11 AM UTC 24 3035031688 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2221522013 Aug 25 11:00:09 AM UTC 24 Aug 25 11:00:12 AM UTC 24 44105555 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2742762584 Aug 25 10:59:43 AM UTC 24 Aug 25 11:00:14 AM UTC 24 4395144919 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.509341551 Aug 25 11:00:11 AM UTC 24 Aug 25 11:00:14 AM UTC 24 14721492 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.710507952 Aug 25 11:00:11 AM UTC 24 Aug 25 11:00:14 AM UTC 24 450263234 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3551041655 Aug 25 10:59:41 AM UTC 24 Aug 25 11:00:16 AM UTC 24 10934152318 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.4072409086 Aug 25 10:59:56 AM UTC 24 Aug 25 11:00:17 AM UTC 24 2562761766 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2624700822 Aug 25 10:59:57 AM UTC 24 Aug 25 11:00:18 AM UTC 24 1394375024 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2461483521 Aug 25 11:00:17 AM UTC 24 Aug 25 11:00:20 AM UTC 24 36266565 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1547198904 Aug 25 11:00:15 AM UTC 24 Aug 25 11:00:22 AM UTC 24 130504552 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1349271855 Aug 25 10:58:47 AM UTC 24 Aug 25 11:00:21 AM UTC 24 11009017699 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3798391014 Aug 25 11:00:11 AM UTC 24 Aug 25 11:00:22 AM UTC 24 2162443441 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.1027451443 Aug 25 11:00:14 AM UTC 24 Aug 25 11:00:23 AM UTC 24 443996475 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.2697681613 Aug 25 11:00:09 AM UTC 24 Aug 25 11:00:23 AM UTC 24 2872692703 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1794055469 Aug 25 11:00:21 AM UTC 24 Aug 25 11:00:24 AM UTC 24 63751635 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2432329799 Aug 25 11:00:12 AM UTC 24 Aug 25 11:00:25 AM UTC 24 551067518 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.232697436 Aug 25 11:00:23 AM UTC 24 Aug 25 11:00:25 AM UTC 24 155553855 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.3388907597 Aug 25 11:00:24 AM UTC 24 Aug 25 11:00:25 AM UTC 24 17039808 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.2808316149 Aug 25 11:00:24 AM UTC 24 Aug 25 11:00:26 AM UTC 24 242282989 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.4225293988 Aug 25 10:59:46 AM UTC 24 Aug 25 11:00:27 AM UTC 24 1167452059 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1783318087 Aug 25 11:00:25 AM UTC 24 Aug 25 11:00:27 AM UTC 24 58201444 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.398723756 Aug 25 11:00:26 AM UTC 24 Aug 25 11:00:28 AM UTC 24 22126325 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.1485865653 Aug 25 11:00:26 AM UTC 24 Aug 25 11:00:29 AM UTC 24 59920306 ps
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