Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34263	1			T8	2		T10	8		T11	8
auto[SpiFlashAddrCfg]	7203	1			T9	3		T10	2		T11	3
auto[SpiFlashAddr3b]	9155	1			T9	2		T10	2		T11	6
auto[SpiFlashAddr4b]	7638	1			T10	2		T11	3		T12	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33170

1

T8

2

T9

5

T11

11

auto[1]

25089

1

T10

14

T11

9

T59

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30522

1

T9

5

T10

4

T11

7

auto[1]

27737

1

T8

2

T10

10

T11

13

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38862	1			T8	2		T10	10		T11	11
values[1]	1149	1			T11	2		T91	2		T49	9
values[2]	1423	1			T9	3		T10	2		T11	1
values[3]	1514	1			T11	1		T12	4		T56	2
values[4]	1437	1			T56	6		T58	1		T185	2
values[5]	1426	1			T12	2		T59	2		T42	2
values[6]	1493	1			T53	2		T42	5		T58	1
values[7]	1399	1			T9	2		T11	3		T18	2
values[8]	9556	1			T10	2		T11	2		T12	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32393

1

T8

2

T10

14

T11

20

auto[1]

25866

1

T9

5

T17

1

T51

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54984

1

T8

2

T9

5

T10

14

write

3275

1

T11

4

T54

4

T42

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18623

1

T8

2

T9

5

T10

2

valids[0x1]

39636

1

T10

12

T11

14

T12

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1590	1			T10	2		T11	2		T12	2
internal_process_ops[0x5a]	1627	1			T10	2		T11	3		T68	6
internal_process_ops[0x05]	20655	1			T10	2		T68	4		T56	2
internal_process_ops[0x35]	1513	1			T10	2		T16	2		T42	1
internal_process_ops[0x15]	1636	1			T10	2		T11	1		T12	2
internal_process_ops[0x03]	1108	1			T18	2		T51	1		T42	1
internal_process_ops[0x0b]	1064	1			T51	2		T42	4		T186	2
internal_process_ops[0x3b]	1093	1			T9	3		T12	2		T16	2
internal_process_ops[0x6b]	1112	1			T11	1		T12	2		T53	2
internal_process_ops[0xbb]	1111	1			T11	1		T12	4		T56	6
internal_process_ops[0xeb]	1077	1			T9	2		T10	2		T12	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56671

1

T8

2

T9

5

T10

14

auto[1]

1588

1

T11

1

T54

4

T42

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55935

1

T8

2

T9

5

T10

14

auto[1]

2324

1

T11

4

T42

5

T55

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11116

1

T8

2

T11

5

T12

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6745

1

T10

8

T11

3

T42

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2135

1

T11

2

T16

2

T56

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1816

1

T10

2

T11

1

T42

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2591

1

T12

4

T18

4

T53

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2227

1

T10

2

T11

3

T59

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2223

1

T11

1

T12

8

T18

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1802

1

T10

2

T11

1

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T91

2

T92

2

T67

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T60

2

T63

1

T67

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

125

1

T66

4

T187

4

T96

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T60

2

T188

1

T65

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T60

2

T189

5

T190

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T42

1

T60

1

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T45

2

T191

2

T97

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

134

1

T61

2

T60

4

T189

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T11

2

T55

2

T62

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

121

1

T11

1

T60

1

T45

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T58

1

T63

1

T45

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

116

1

T54

4

T67

2

T189

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

128

1

T60

2

T63

1

T192

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T42

2

T60

1

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T11

1

T60

1

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T42

1

T60

1

T64

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9113

1

T48

4

T49

56

T50

14

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6447

1

T48

65

T49

33

T50

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1255

1

T9

3

T17

1

T52

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1216

1

T49

7

T50

4

T108

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1747

1

T9

2

T51

5

T52

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1736

1

T48

6

T49

14

T50

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1376

1

T51

1

T48

1

T49

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1439

1

T48

1

T49

16

T50

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T46

4

T47

2

T193

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T48

3

T49

1

T50

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T46

1

T47

2

T100

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T49

2

T46

1

T194

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T47

2

T100

1

T195

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T108

1

T46

2

T95

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T49

1

T46

5

T47

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T48

2

T46

1

T47

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T49

1

T46

2

T47

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T49

2

T193

2

T100

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T46

1

T47

2

T194

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T49

7

T46

1

T100

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

84

1

T49

2

T47

6

T100

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T47

1

T196

2

T156

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

108

1

T49

1

T50

1

T46

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T46

6

T47

5

T193

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3812	1			T8	2		T11	4		T18	2
auto[0]	values[0]	valids[0x1]	17096	1			T10	10		T11	7		T12	4
auto[0]	values[1]	valids[0x1]	640	1			T11	2		T91	2		T60	8
auto[0]	values[2]	valids[0x0]	511	1			T11	1		T12	4		T16	2
auto[0]	values[2]	valids[0x1]	315	1			T10	2		T42	6		T60	2
auto[0]	values[3]	valids[0x0]	576	1			T11	1		T12	4		T56	2
auto[0]	values[3]	valids[0x1]	330	1			T62	2		T63	1		T45	4
auto[0]	values[4]	valids[0x0]	552	1			T56	6		T185	2		T197	2
auto[0]	values[4]	valids[0x1]	301	1			T58	1		T60	3		T198	2
auto[0]	values[5]	valids[0x0]	565	1			T12	2		T42	2		T55	2
auto[0]	values[5]	valids[0x1]	275	1			T59	2		T199	2		T197	4
auto[0]	values[6]	valids[0x0]	607	1			T53	2		T42	5		T200	2
auto[0]	values[6]	valids[0x1]	326	1			T58	1		T60	6		T63	4
auto[0]	values[7]	valids[0x0]	545	1			T18	2		T56	6		T42	3
auto[0]	values[7]	valids[0x1]	301	1			T11	3		T68	6		T42	1
auto[0]	values[8]	valids[0x0]	3566	1			T10	2		T12	2		T53	2
auto[0]	values[8]	valids[0x1]	2075	1			T11	2		T18	4		T42	5
auto[1]	values[0]	valids[0x0]	3568	1			T48	3		T49	32		T50	15
auto[1]	values[0]	valids[0x1]	14386	1			T51	1		T48	73		T49	78
auto[1]	values[1]	valids[0x1]	509	1			T49	9		T50	1		T108	2
auto[1]	values[2]	valids[0x0]	336	1			T9	3		T49	2		T50	5
auto[1]	values[2]	valids[0x1]	261	1			T51	2		T50	1		T46	3
auto[1]	values[3]	valids[0x0]	348	1			T48	4		T49	5		T108	2
auto[1]	values[3]	valids[0x1]	260	1			T49	1		T116	2		T46	2
auto[1]	values[4]	valids[0x0]	330	1			T49	3		T50	1		T108	3
auto[1]	values[4]	valids[0x1]	254	1			T49	2		T50	1		T116	4
auto[1]	values[5]	valids[0x0]	336	1			T49	3		T116	1		T46	2
auto[1]	values[5]	valids[0x1]	250	1			T46	4		T47	3		T100	4
auto[1]	values[6]	valids[0x0]	331	1			T52	1		T49	8		T50	1
auto[1]	values[6]	valids[0x1]	229	1			T49	1		T116	1		T46	3
auto[1]	values[7]	valids[0x0]	314	1			T9	2		T49	2		T166	1
auto[1]	values[7]	valids[0x1]	239	1			T49	2		T50	3		T108	1
auto[1]	values[8]	valids[0x0]	2326	1			T17	1		T51	3		T52	1
auto[1]	values[8]	valids[0x1]	1589	1			T48	1		T49	12		T126	1