Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3346297

1

T8

1

T9

833

T10

1

auto[1]

29710

1

T11

27

T42

89

T55

60

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910562

1

T8

1

T9

833

T10

1

auto[1]

2465445

1

T11

2588

T16

38

T69

8

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	617777	1			T8	1		T9	394		T10	1
auto[524288:1048575]	452056	1			T12	519		T19	8		T22	528
auto[1048576:1572863]	395794	1			T11	5		T12	448		T16	20
auto[1572864:2097151]	405062	1			T9	23		T22	1		T51	11
auto[2097152:2621439]	366712	1			T9	17		T11	2		T12	124
auto[2621440:3145727]	363699	1			T11	2		T12	348		T22	515
auto[3145728:3670015]	417917	1			T11	9		T22	1478		T51	2
auto[3670016:4194303]	356990	1			T9	399		T11	13		T12	1104

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2498296

1

T8

1

T9

15

T10

1

auto[1]

877711

1

T9

818

T11

1

T12

3214

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2880655

1

T8

1

T9

833

T10

1

auto[1]

495352

1

T22

17

T42

543

T58

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	170639	1			T8	1		T9	394		T10	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	375938	1			T11	2588		T16	19		T42	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	115906	1			T12	519		T19	8		T22	528
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	250127	1			T48	39		T49	3097		T60	769
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	114257	1			T11	2		T12	448		T16	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	225374	1			T16	19		T69	2		T48	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112529	1			T9	23		T22	1		T51	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	239414	1			T48	2		T186	116		T49	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	78408	1			T9	17		T11	2		T12	124
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	230206	1			T186	13		T49	1469		T60	385
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	97511	1			T12	348		T22	515		T51	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	196231	1			T69	6		T42	1182		T60	264
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	126651	1			T22	1478		T51	2		T68	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	243643	1			T58	512		T49	1548		T60	2220
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	81444	1			T9	399		T11	6		T12	1104
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	198750	1			T49	512		T60	384		T45	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	1405	1			T22	2		T45	9		T67	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	64353	1			T45	4201		T67	1		T189	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	899	1			T49	2		T60	6		T50	12
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	81504	1			T49	11		T60	259		T46	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1571	1			T42	27		T58	1		T116	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51349	1			T42	512		T45	1		T189	2564
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2049	1			T112	152		T50	7		T46	18
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47138	1			T46	256		T47	896		T95	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	670	1			T49	2		T46	26		T47	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53387	1			T49	1512		T116	256		T46	260
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	824	1			T46	2		T47	3		T100	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	66332	1			T100	768		T67	256		T95	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1311	1			T60	2		T50	7		T45	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42302	1			T60	1043		T45	1		T47	387
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	884	1			T22	15		T58	2		T112	195
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	73291	1			T46	2477		T47	908		T100	262
auto[1]	auto[0]	auto[0:524287]	auto[0]	478	1			T11	6		T55	2		T58	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4271	1			T55	58		T58	7		T62	21
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	341	1			T48	1		T60	1		T63	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2771	1			T48	23		T60	22		T63	36
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	359	1			T11	3		T42	14		T48	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1801	1			T48	13		T49	6		T116	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	376	1			T48	2		T49	1		T60	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2325	1			T48	16		T49	3		T60	75
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	359	1			T49	1		T60	1		T108	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2923	1			T49	1		T60	21		T46	128
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	300	1			T11	2		T42	16		T60	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1766	1			T42	47		T60	29		T46	128
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	353	1			T11	9		T60	4		T45	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2927	1			T60	34		T45	14		T46	128
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	382	1			T11	7		T42	8		T50	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1895	1			T46	100		T47	24		T100	27
auto[1]	auto[1]	auto[0:524287]	auto[0]	118	1			T45	3		T67	1		T196	7
auto[1]	auto[1]	auto[0:524287]	auto[1]	575	1			T45	28		T67	4		T224	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	78	1			T49	1		T60	3		T47	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	430	1			T49	5		T60	92		T47	46
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	64	1			T42	4		T45	1		T46	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1019	1			T45	27		T189	35		T239	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	85	1			T269	1		T239	2		T243	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1146	1			T269	21		T239	7		T243	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	71	1			T196	5		T187	3		T191	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	688	1			T187	151		T191	170		T99	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	87	1			T189	1		T37	1		T227	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	648	1			T189	27		T37	16		T227	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	92	1			T45	1		T47	3		T95	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	638	1			T45	47		T47	85		T95	24
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	61	1			T100	3		T67	2		T196	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	283	1			T100	15		T67	18		T227	13

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1984848	1			T8	1		T9	15		T10	1
auto[0]	auto[0]	auto[1]	872180	1			T9	818		T12	3214		T16	58
auto[0]	auto[1]	auto[0]	484363	1			T22	3		T42	539		T58	3
auto[0]	auto[1]	auto[1]	4906	1			T22	14		T112	81		T60	3
auto[1]	auto[0]	auto[0]	23120	1			T11	26		T42	84		T55	58
auto[1]	auto[0]	auto[1]	507	1			T11	1		T42	1		T55	2
auto[1]	auto[1]	auto[0]	5965	1			T42	4		T49	6		T60	95
auto[1]	auto[1]	auto[1]	118	1			T45	1		T47	2		T100	1