Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2866173	1			T1	1		T3	1		T4	1
all_pins[1]	2866173	1			T1	1		T3	1		T4	1
all_pins[2]	2866173	1			T1	1		T3	1		T4	1
all_pins[3]	2866173	1			T1	1		T3	1		T4	1
all_pins[4]	2866173	1			T1	1		T3	1		T4	1
all_pins[5]	2866173	1			T1	1		T3	1		T4	1
all_pins[6]	2866173	1			T1	1		T3	1		T4	1
all_pins[7]	2866173	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22735992	1			T1	8		T3	8		T4	8
values[0x1]	193392	1			T32	40		T35	46		T95	113
transitions[0x0=>0x1]	191459	1			T32	34		T35	38		T95	45
transitions[0x1=>0x0]	191473	1			T32	34		T35	38		T95	45

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2865134	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	1039	1			T32	3		T35	7		T95	40
all_pins[0]	transitions[0x0=>0x1]	472	1			T32	3		T35	6		T95	5
all_pins[0]	transitions[0x1=>0x0]	198	1			T32	5		T35	3		T95	3
all_pins[1]	values[0x0]	2865408	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	765	1			T32	5		T35	4		T95	38
all_pins[1]	transitions[0x0=>0x1]	495	1			T32	5		T35	2		T95	5
all_pins[1]	transitions[0x1=>0x0]	227	1			T32	5		T35	6		T36	4
all_pins[2]	values[0x0]	2865676	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	497	1			T32	5		T35	8		T95	33
all_pins[2]	transitions[0x0=>0x1]	432	1			T32	4		T35	6		T95	33
all_pins[2]	transitions[0x1=>0x0]	142	1			T32	6		T35	6		T36	4
all_pins[3]	values[0x0]	2865966	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	207	1			T32	7		T35	8		T36	6
all_pins[3]	transitions[0x0=>0x1]	163	1			T32	7		T35	8		T36	4
all_pins[3]	transitions[0x1=>0x0]	158	1			T32	3		T35	5		T95	2
all_pins[4]	values[0x0]	2865971	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	202	1			T32	3		T35	5		T95	2
all_pins[4]	transitions[0x0=>0x1]	158	1			T32	3		T35	5		T95	2
all_pins[4]	transitions[0x1=>0x0]	958	1			T32	7		T35	4		T36	3
all_pins[5]	values[0x0]	2865171	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	1002	1			T32	7		T35	4		T36	5
all_pins[5]	transitions[0x0=>0x1]	164	1			T32	4		T35	4		T36	4
all_pins[5]	transitions[0x1=>0x0]	188659	1			T32	4		T35	1		T36	2
all_pins[6]	values[0x0]	2676676	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	189497	1			T32	7		T35	1		T36	3
all_pins[6]	transitions[0x0=>0x1]	189450	1			T32	6		T36	1		T37	9871
all_pins[6]	transitions[0x1=>0x0]	136	1			T32	2		T35	8		T36	4
all_pins[7]	values[0x0]	2865990	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	183	1			T32	3		T35	9		T36	6
all_pins[7]	transitions[0x0=>0x1]	125	1			T32	2		T35	7		T36	4
all_pins[7]	transitions[0x1=>0x0]	995	1			T32	2		T35	5		T95	40