Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18916

1

T8

2

T11

11

T12

16

auto[1]

13477

1

T10

14

T11

9

T59

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4102	1			T69	8		T60	81		T198	16
values[1]	4697	1			T68	14		T55	70		T275	4
values[2]	4382	1			T57	12		T186	14		T60	108
values[3]	4561	1			T11	20		T42	20		T58	29
values[4]	3875	1			T18	12		T22	4		T42	20
values[5]	3761	1			T16	6		T20	2		T244	4
values[6]	3364	1			T8	2		T56	22		T262	10
values[7]	3651	1			T10	14		T12	16		T19	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3963	1			T10	14		T11	20		T262	10
values[1]	3972	1			T19	6		T42	20		T57	12
values[2]	3630	1			T56	22		T58	29		T185	6
values[3]	3676	1			T53	6		T42	20		T244	4
values[4]	4517	1			T18	12		T59	4		T68	14
values[5]	4467	1			T16	6		T197	18		T91	83
values[6]	3790	1			T8	2		T22	4		T69	8
values[7]	4378	1			T12	16		T20	2		T54	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	266	1			T60	30		T198	16		T189	46
auto[0]	values[0]	values[1]	348	1			T66	5		T76	13		T238	20
auto[0]	values[0]	values[2]	324	1			T276	2		T66	14		T277	16
auto[0]	values[0]	values[3]	295	1			T189	99		T278	12		T279	14
auto[0]	values[0]	values[4]	349	1			T67	10		T187	12		T76	10
auto[0]	values[0]	values[5]	435	1			T228	4		T280	2		T242	11
auto[0]	values[0]	values[6]	158	1			T69	8		T218	16		T281	17
auto[0]	values[0]	values[7]	253	1			T60	11		T251	8		T187	10
auto[0]	values[1]	values[0]	397	1			T266	99		T282	28		T245	12
auto[0]	values[1]	values[1]	314	1			T191	11		T97	8		T245	5
auto[0]	values[1]	values[2]	445	1			T60	134		T237	14		T86	6
auto[0]	values[1]	values[3]	373	1			T60	5		T283	4		T239	24
auto[0]	values[1]	values[4]	252	1			T68	14		T284	8		T285	16
auto[0]	values[1]	values[5]	340	1			T197	18		T96	24		T97	15
auto[0]	values[1]	values[6]	438	1			T55	70		T275	4		T286	12
auto[0]	values[1]	values[7]	370	1			T67	12		T189	11		T287	4
auto[0]	values[2]	values[0]	249	1			T288	2		T269	28		T253	18
auto[0]	values[2]	values[1]	225	1			T57	12		T289	2		T221	11
auto[0]	values[2]	values[2]	202	1			T60	12		T232	8		T76	12
auto[0]	values[2]	values[3]	328	1			T67	13		T247	24		T97	11
auto[0]	values[2]	values[4]	331	1			T227	11		T210	10		T245	9
auto[0]	values[2]	values[5]	270	1			T60	17		T45	57		T273	16
auto[0]	values[2]	values[6]	397	1			T220	24		T236	12		T290	16
auto[0]	values[2]	values[7]	525	1			T186	14		T92	80		T215	11
auto[0]	values[3]	values[0]	288	1			T11	11		T188	75		T209	15
auto[0]	values[3]	values[1]	383	1			T62	39		T291	2		T239	17
auto[0]	values[3]	values[2]	283	1			T58	11		T292	12		T96	26
auto[0]	values[3]	values[3]	272	1			T191	9		T242	15		T263	12
auto[0]	values[3]	values[4]	221	1			T188	2		T96	12		T227	32
auto[0]	values[3]	values[5]	390	1			T239	32		T242	11		T253	16
auto[0]	values[3]	values[6]	300	1			T200	2		T264	8		T76	14
auto[0]	values[3]	values[7]	446	1			T42	10		T60	38		T189	13
auto[0]	values[4]	values[0]	408	1			T259	8		T176	19		T281	23
auto[0]	values[4]	values[1]	332	1			T42	12		T245	9		T243	11
auto[0]	values[4]	values[2]	248	1			T242	14		T157	13		T222	33
auto[0]	values[4]	values[3]	275	1			T293	2		T45	14		T83	6
auto[0]	values[4]	values[4]	385	1			T18	12		T246	12		T96	13
auto[0]	values[4]	values[5]	176	1			T45	13		T96	11		T97	22
auto[0]	values[4]	values[6]	299	1			T22	4		T252	18		T191	14
auto[0]	values[4]	values[7]	165	1			T190	18		T294	2		T96	17
auto[0]	values[5]	values[0]	246	1			T60	16		T295	8		T210	10
auto[0]	values[5]	values[1]	333	1			T296	14		T225	12		T297	48
auto[0]	values[5]	values[2]	202	1			T60	40		T192	6		T97	13
auto[0]	values[5]	values[3]	233	1			T244	4		T233	8		T298	10
auto[0]	values[5]	values[4]	421	1			T96	61		T243	18		T299	94
auto[0]	values[5]	values[5]	370	1			T16	6		T91	83		T269	10
auto[0]	values[5]	values[6]	168	1			T213	2		T187	13		T114	4
auto[0]	values[5]	values[7]	309	1			T20	2		T188	9		T67	15
auto[0]	values[6]	values[0]	190	1			T262	10		T112	8		T63	46
auto[0]	values[6]	values[1]	305	1			T300	10		T67	33		T277	12
auto[0]	values[6]	values[2]	239	1			T56	22		T239	9		T301	8
auto[0]	values[6]	values[3]	120	1			T67	11		T96	7		T76	11
auto[0]	values[6]	values[4]	333	1			T302	14		T63	8		T45	12
auto[0]	values[6]	values[5]	284	1			T45	28		T191	16		T277	11
auto[0]	values[6]	values[6]	350	1			T8	2		T227	12		T253	46
auto[0]	values[6]	values[7]	123	1			T60	12		T303	4		T304	6
auto[0]	values[7]	values[0]	289	1			T66	10		T305	10		T76	33
auto[0]	values[7]	values[1]	207	1			T19	6		T188	12		T97	6
auto[0]	values[7]	values[2]	319	1			T45	10		T223	175		T306	33
auto[0]	values[7]	values[3]	227	1			T53	6		T42	7		T307	4
auto[0]	values[7]	values[4]	148	1			T66	11		T215	12		T253	11
auto[0]	values[7]	values[5]	296	1			T63	11		T269	9		T234	20
auto[0]	values[7]	values[6]	143	1			T308	8		T96	8		T227	7
auto[0]	values[7]	values[7]	306	1			T12	16		T67	15		T96	31
auto[1]	values[0]	values[0]	167	1			T60	9		T189	11		T239	12
auto[1]	values[0]	values[1]	191	1			T66	15		T76	7		T222	34
auto[1]	values[0]	values[2]	126	1			T66	6		T277	11		T309	10
auto[1]	values[0]	values[3]	130	1			T189	5		T306	7		T219	30
auto[1]	values[0]	values[4]	489	1			T67	20		T187	8		T76	10
auto[1]	values[0]	values[5]	241	1			T242	9		T243	51		T310	10
auto[1]	values[0]	values[6]	94	1			T218	6		T281	3		T270	7
auto[1]	values[0]	values[7]	236	1			T60	31		T187	10		T297	7
auto[1]	values[1]	values[0]	190	1			T266	7		T245	8		T174	7
auto[1]	values[1]	values[1]	213	1			T191	9		T97	31		T245	15
auto[1]	values[1]	values[2]	299	1			T199	4		T60	10		T311	11
auto[1]	values[1]	values[3]	181	1			T60	15		T239	8		T312	12
auto[1]	values[1]	values[4]	139	1			T65	18		T263	9		T299	17
auto[1]	values[1]	values[5]	334	1			T96	8		T97	26		T227	22
auto[1]	values[1]	values[6]	109	1			T96	12		T97	2		T76	8
auto[1]	values[1]	values[7]	303	1			T268	8		T67	18		T189	9
auto[1]	values[2]	values[0]	257	1			T269	63		T313	10		T253	30
auto[1]	values[2]	values[1]	164	1			T221	9		T314	26		T315	8
auto[1]	values[2]	values[2]	193	1			T60	76		T76	8		T241	6
auto[1]	values[2]	values[3]	139	1			T67	8		T97	9		T316	9
auto[1]	values[2]	values[4]	375	1			T227	79		T210	10		T245	11
auto[1]	values[2]	values[5]	289	1			T60	3		T317	4		T45	11
auto[1]	values[2]	values[6]	304	1			T240	9		T318	79		T306	12
auto[1]	values[2]	values[7]	134	1			T215	9		T210	2		T319	22
auto[1]	values[3]	values[0]	175	1			T11	9		T188	6		T209	5
auto[1]	values[3]	values[1]	153	1			T239	3		T215	30		T320	12
auto[1]	values[3]	values[2]	307	1			T58	18		T96	19		T191	10
auto[1]	values[3]	values[3]	155	1			T191	11		T242	5		T263	13
auto[1]	values[3]	values[4]	202	1			T188	18		T96	8		T227	19
auto[1]	values[3]	values[5]	207	1			T239	11		T242	9		T253	4
auto[1]	values[3]	values[6]	171	1			T76	6		T297	2		T210	11
auto[1]	values[3]	values[7]	608	1			T42	10		T60	12		T189	171
auto[1]	values[4]	values[0]	215	1			T176	4		T281	8		T321	10
auto[1]	values[4]	values[1]	221	1			T42	8		T245	11		T243	66
auto[1]	values[4]	values[2]	128	1			T185	6		T242	6		T157	7
auto[1]	values[4]	values[3]	292	1			T45	30		T297	6		T240	2
auto[1]	values[4]	values[4]	241	1			T96	12		T269	4		T253	8
auto[1]	values[4]	values[5]	179	1			T45	7		T96	44		T97	7
auto[1]	values[4]	values[6]	150	1			T191	6		T215	9		T221	7
auto[1]	values[4]	values[7]	161	1			T96	5		T239	3		T245	5
auto[1]	values[5]	values[0]	216	1			T60	4		T210	10		T310	9
auto[1]	values[5]	values[1]	197	1			T297	8		T216	11		T174	9
auto[1]	values[5]	values[2]	71	1			T60	3		T97	20		T215	4
auto[1]	values[5]	values[3]	113	1			T248	3		T297	18		T322	5
auto[1]	values[5]	values[4]	215	1			T64	12		T96	6		T243	12
auto[1]	values[5]	values[5]	254	1			T269	10		T248	13		T267	11
auto[1]	values[5]	values[6]	266	1			T187	7		T216	19		T174	21
auto[1]	values[5]	values[7]	147	1			T188	11		T67	9		T239	10
auto[1]	values[6]	values[0]	119	1			T63	11		T217	22		T176	12
auto[1]	values[6]	values[1]	142	1			T67	3		T255	18		T277	8
auto[1]	values[6]	values[2]	125	1			T323	4		T239	17		T324	4
auto[1]	values[6]	values[3]	198	1			T67	29		T96	19		T76	9
auto[1]	values[6]	values[4]	319	1			T63	50		T45	64		T97	61
auto[1]	values[6]	values[5]	127	1			T45	20		T191	4		T277	15
auto[1]	values[6]	values[6]	278	1			T227	8		T253	6		T297	2
auto[1]	values[6]	values[7]	112	1			T60	8		T221	13		T311	12
auto[1]	values[7]	values[0]	291	1			T10	14		T66	10		T76	7
auto[1]	values[7]	values[1]	244	1			T188	11		T97	66		T215	46
auto[1]	values[7]	values[2]	119	1			T45	10		T325	10		T223	15
auto[1]	values[7]	values[3]	345	1			T42	13		T187	5		T215	50
auto[1]	values[7]	values[4]	97	1			T59	4		T66	9		T215	8
auto[1]	values[7]	values[5]	275	1			T63	9		T269	67		T253	6
auto[1]	values[7]	values[6]	165	1			T96	12		T227	13		T210	10
auto[1]	values[7]	values[7]	180	1			T54	4		T61	8		T67	5