Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	498	1			T11	1		T12	8		T42	1
auto[ReadAddrCrossIntoMailbox]	336	1			T42	2		T262	2		T60	7
auto[ReadAddrCrossOutOfMailbox]	347	1			T42	1		T262	2		T60	2
auto[ReadAddrCrossAllMailbox]	244	1			T11	1		T200	2		T262	4
auto[ReadAddrOutsideMailbox]	3657	1			T10	2		T12	4		T16	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T10

1

T12

6

T16

1

auto[1]

2591

1

T10

1

T11

2

T12

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	853	1			T18	2		T42	1		T58	1
read_ops[0x0b]	826	1			T42	4		T186	2		T60	6
read_ops[0x3b]	860	1			T12	2		T16	2		T56	6
read_ops[0x6b]	883	1			T11	1		T12	2		T53	2
read_ops[0xbb]	846	1			T11	1		T12	4		T56	6
read_ops[0xeb]	814	1			T10	2		T12	4		T18	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T60	1		T232	3		T97	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T60	1		T63	1		T232	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T60	2		T97	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T187	1		T96	1		T269	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T76	1		T297	1		T216	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T67	1		T227	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T287	1		T97	1		T253	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T60	1		T287	1		T96	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T18	1		T58	1		T62	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T18	1		T42	1		T62	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T96	1		T222	1		T174	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T188	1		T297	2		T311	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T60	2		T45	1		T97	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T63	1		T96	2		T216	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T63	1		T96	2		T97	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T191	1		T239	1		T227	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T67	1		T327	1		T97	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T327	1		T76	1		T216	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T186	1		T60	2		T92	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T42	4		T186	1		T60	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T96	1		T97	2		T76	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T210	3		T222	1		T221	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T66	1		T96	1		T216	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T188	1		T97	2		T227	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T262	1		T60	1		T188	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T262	1		T188	1		T96	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T262	1		T60	1		T216	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T262	1		T45	1		T96	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T12	1		T16	1		T56	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T12	1		T16	1		T56	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T57	1		T262	1		T66	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	53	1			T42	1		T57	1		T262	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T96	1		T97	1		T215	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T42	1		T96	1		T297	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T96	1		T191	1		T227	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T96	2		T97	1		T222	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T297	1		T328	1		T329	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T11	1		T269	1		T239	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	341	1			T12	1		T53	1		T56	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T12	1		T53	1		T56	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T12	2		T57	1		T63	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	51	1			T11	1		T12	2		T57	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T60	2		T67	1		T329	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T60	1		T96	1		T97	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T45	1		T188	1		T67	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T67	1		T189	2		T76	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T200	1		T76	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T200	1		T45	1		T188	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T56	3		T244	1		T186	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T56	3		T42	1		T244	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T12	2		T45	1		T189	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T12	2		T96	1		T97	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T42	1		T262	1		T222	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T262	1		T269	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T42	1		T67	1		T327	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T60	1		T63	3		T327	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T262	1		T45	2		T66	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T262	1		T328	1		T330	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T10	1		T18	1		T53	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T10	1		T18	1		T53	1