Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3319	1			T18	12		T19	6		T262	10
values[1]	4771	1			T11	20		T54	4		T68	14
values[2]	3888	1			T200	2		T197	18		T60	42
values[3]	3787	1			T302	14		T91	83		T60	131
values[4]	4382	1			T20	2		T22	4		T53	6
values[5]	3536	1			T10	14		T12	16		T59	4
values[6]	4510	1			T42	20		T58	29		T62	39
values[7]	4200	1			T8	2		T16	6		T244	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4205	1			T18	12		T54	4		T57	12
values[1]	4178	1			T11	20		T16	6		T53	6
values[2]	4525	1			T8	2		T22	4		T59	4
values[3]	3381	1			T10	14		T197	18		T60	171
values[4]	4008	1			T20	2		T55	70		T262	10
values[5]	4528	1			T12	16		T69	8		T91	83
values[6]	3991	1			T42	40		T185	6		T60	39
values[7]	3577	1			T19	6		T302	14		T233	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31549

1

T8

2

T10

14

T11

19

auto[1]

844

1

T11

1

T54

4

T42

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	432	1			T18	12		T199	4		T67	24
auto[0]	values[0]	values[1]	367	1			T283	4		T239	25		T221	20
auto[0]	values[0]	values[2]	511	1			T292	12		T305	10		T210	55
auto[0]	values[0]	values[3]	498	1			T65	12		T189	104		T83	6
auto[0]	values[0]	values[4]	266	1			T262	10		T275	4		T276	2
auto[0]	values[0]	values[5]	499	1			T298	10		T331	20		T218	24
auto[0]	values[0]	values[6]	258	1			T185	6		T66	20		T191	19
auto[0]	values[0]	values[7]	376	1			T19	6		T97	38		T115	14
auto[0]	values[1]	values[0]	594	1			T288	2		T190	18		T209	20
auto[0]	values[1]	values[1]	537	1			T11	19		T112	8		T269	59
auto[0]	values[1]	values[2]	926	1			T68	14		T187	20		T76	23
auto[0]	values[1]	values[3]	390	1			T192	6		T67	20		T76	25
auto[0]	values[1]	values[4]	562	1			T55	70		T186	14		T189	54
auto[0]	values[1]	values[5]	454	1			T255	18		T242	41		T216	20
auto[0]	values[1]	values[6]	537	1			T45	19		T191	19		T242	20
auto[0]	values[1]	values[7]	653	1			T233	8		T96	20		T76	20
auto[0]	values[2]	values[0]	379	1			T45	68		T188	20		T239	17
auto[0]	values[2]	values[1]	428	1			T200	2		T247	24		T280	2
auto[0]	values[2]	values[2]	566	1			T66	19		T67	29		T258	10
auto[0]	values[2]	values[3]	250	1			T197	18		T96	19		T332	18
auto[0]	values[2]	values[4]	621	1			T67	34		T246	12		T227	86
auto[0]	values[2]	values[5]	755	1			T60	41		T66	20		T239	31
auto[0]	values[2]	values[6]	509	1			T213	2		T269	20		T297	20
auto[0]	values[2]	values[7]	275	1			T188	20		T333	16		T334	2
auto[0]	values[3]	values[0]	428	1			T215	125		T335	16		T174	46
auto[0]	values[3]	values[1]	451	1			T187	18		T215	49		T210	20
auto[0]	values[3]	values[2]	372	1			T45	43		T189	20		T253	20
auto[0]	values[3]	values[3]	478	1			T60	129		T63	58		T252	18
auto[0]	values[3]	values[4]	335	1			T64	8		T287	4		T336	6
auto[0]	values[3]	values[5]	744	1			T91	83		T326	22		T96	101
auto[0]	values[3]	values[6]	454	1			T45	75		T76	37		T222	39
auto[0]	values[3]	values[7]	426	1			T302	14		T337	2		T338	22
auto[0]	values[4]	values[0]	546	1			T220	24		T227	32		T76	19
auto[0]	values[4]	values[1]	654	1			T53	6		T60	139		T45	20
auto[0]	values[4]	values[2]	516	1			T22	4		T42	20		T61	6
auto[0]	values[4]	values[3]	461	1			T67	21		T304	6		T294	2
auto[0]	values[4]	values[4]	614	1			T20	2		T63	56		T295	8
auto[0]	values[4]	values[5]	512	1			T60	20		T245	20		T243	76
auto[0]	values[4]	values[6]	500	1			T42	19		T66	20		T209	19
auto[0]	values[4]	values[7]	463	1			T228	4		T303	4		T289	2
auto[0]	values[5]	values[0]	523	1			T57	12		T307	4		T273	16
auto[0]	values[5]	values[1]	292	1			T56	22		T297	112		T339	10
auto[0]	values[5]	values[2]	372	1			T59	4		T60	20		T210	20
auto[0]	values[5]	values[3]	506	1			T10	14		T63	20		T209	20
auto[0]	values[5]	values[4]	500	1			T188	23		T191	20		T97	60
auto[0]	values[5]	values[5]	462	1			T12	16		T69	8		T291	2
auto[0]	values[5]	values[6]	424	1			T60	37		T67	29		T187	38
auto[0]	values[5]	values[7]	366	1			T251	8		T267	81		T240	20
auto[0]	values[6]	values[0]	588	1			T60	48		T286	12		T96	66
auto[0]	values[6]	values[1]	1071	1			T62	39		T293	2		T92	80
auto[0]	values[6]	values[2]	557	1			T58	29		T198	16		T97	38
auto[0]	values[6]	values[3]	296	1			T60	40		T340	45		T341	22
auto[0]	values[6]	values[4]	739	1			T264	8		T114	4		T215	20
auto[0]	values[6]	values[5]	319	1			T97	31		T76	19		T243	60
auto[0]	values[6]	values[6]	507	1			T42	17		T268	8		T269	75
auto[0]	values[6]	values[7]	332	1			T254	12		T282	28		T313	10
auto[0]	values[7]	values[0]	598	1			T227	20		T76	20		T342	10
auto[0]	values[7]	values[1]	282	1			T16	6		T244	4		T240	23
auto[0]	values[7]	values[2]	582	1			T8	2		T317	4		T188	80
auto[0]	values[7]	values[3]	420	1			T96	54		T97	20		T215	39
auto[0]	values[7]	values[4]	249	1			T45	20		T96	19		T343	22
auto[0]	values[7]	values[5]	676	1			T266	102		T239	41		T253	20
auto[0]	values[7]	values[6]	712	1			T67	39		T96	20		T269	71
auto[0]	values[7]	values[7]	579	1			T96	25		T215	57		T76	31
auto[1]	values[0]	values[0]	17	1			T216	1		T240	4		T321	2
auto[1]	values[0]	values[1]	9	1			T239	1		T245	2		T263	1
auto[1]	values[0]	values[2]	28	1			T210	5		T221	5		T319	10
auto[1]	values[0]	values[3]	20	1			T65	6		T221	3		T270	4
auto[1]	values[0]	values[4]	10	1			T176	2		T159	2		T344	3
auto[1]	values[0]	values[5]	12	1			T218	2		T345	1		T281	2
auto[1]	values[0]	values[6]	7	1			T191	1		T241	1		T346	2
auto[1]	values[0]	values[7]	9	1			T97	1		T174	4		T347	1
auto[1]	values[1]	values[0]	16	1			T54	4		T97	5		T277	1
auto[1]	values[1]	values[1]	12	1			T11	1		T239	2		T97	2
auto[1]	values[1]	values[2]	20	1			T310	1		T176	1		T348	3
auto[1]	values[1]	values[3]	8	1			T76	1		T241	1		T349	1
auto[1]	values[1]	values[4]	20	1			T189	3		T215	3		T242	1
auto[1]	values[1]	values[5]	12	1			T242	1		T350	4		T158	1
auto[1]	values[1]	values[6]	13	1			T45	1		T191	1		T297	1
auto[1]	values[1]	values[7]	17	1			T297	3		T174	5		T218	1
auto[1]	values[2]	values[0]	16	1			T239	3		T351	6		T352	3
auto[1]	values[2]	values[1]	7	1			T210	1		T263	1		T353	1
auto[1]	values[2]	values[2]	12	1			T66	1		T67	1		T222	1
auto[1]	values[2]	values[3]	8	1			T96	1		T267	1		T354	1
auto[1]	values[2]	values[4]	26	1			T67	2		T227	4		T222	5
auto[1]	values[2]	values[5]	18	1			T60	1		T239	1		T240	2
auto[1]	values[2]	values[6]	8	1			T210	1		T355	1		T80	3
auto[1]	values[2]	values[7]	10	1			T347	5		T356	2		T357	2
auto[1]	values[3]	values[0]	10	1			T215	1		T335	2		T174	1
auto[1]	values[3]	values[1]	7	1			T187	2		T215	1		T311	1
auto[1]	values[3]	values[2]	13	1			T45	1		T216	2		T257	1
auto[1]	values[3]	values[3]	6	1			T60	2		T174	2		T267	2
auto[1]	values[3]	values[4]	17	1			T64	4		T243	2		T174	1
auto[1]	values[3]	values[5]	11	1			T96	1		T241	2		T158	2
auto[1]	values[3]	values[6]	17	1			T45	1		T76	3		T358	1
auto[1]	values[3]	values[7]	18	1			T222	1		T176	4		T359	2
auto[1]	values[4]	values[0]	17	1			T227	2		T76	1		T226	4
auto[1]	values[4]	values[1]	19	1			T60	5		T97	6		T297	3
auto[1]	values[4]	values[2]	11	1			T61	2		T174	1		T219	3
auto[1]	values[4]	values[3]	11	1			T96	4		T245	1		T306	1
auto[1]	values[4]	values[4]	15	1			T63	1		T245	7		T176	1
auto[1]	values[4]	values[5]	16	1			T243	1		T348	1		T316	2
auto[1]	values[4]	values[6]	12	1			T42	1		T209	1		T96	1
auto[1]	values[4]	values[7]	15	1			T191	5		T243	1		T318	2
auto[1]	values[5]	values[0]	14	1			T96	1		T216	2		T243	2
auto[1]	values[5]	values[1]	11	1			T297	4		T360	3		T361	2
auto[1]	values[5]	values[2]	2	1			T362	1		T161	1		-	-
auto[1]	values[5]	values[3]	12	1			T245	2		T218	4		T363	1
auto[1]	values[5]	values[4]	13	1			T97	3		T364	2		T174	1
auto[1]	values[5]	values[5]	10	1			T263	1		T267	2		T318	1
auto[1]	values[5]	values[6]	13	1			T60	2		T67	1		T187	2
auto[1]	values[5]	values[7]	16	1			T306	1		T365	2		T271	2
auto[1]	values[6]	values[0]	15	1			T60	2		T96	1		T218	1
auto[1]	values[6]	values[1]	17	1			T189	5		T239	2		T240	2
auto[1]	values[6]	values[2]	18	1			T97	3		T76	1		T315	1
auto[1]	values[6]	values[3]	8	1			T257	2		T230	1		T366	2
auto[1]	values[6]	values[4]	18	1			T263	1		T318	2		T176	4
auto[1]	values[6]	values[5]	6	1			T97	2		T76	1		T243	1
auto[1]	values[6]	values[6]	11	1			T42	3		T269	1		T367	2
auto[1]	values[6]	values[7]	8	1			T240	1		T345	1		T368	1
auto[1]	values[7]	values[0]	12	1			T253	1		T263	1		T345	3
auto[1]	values[7]	values[1]	14	1			T240	3		T231	2		T369	2
auto[1]	values[7]	values[2]	19	1			T188	1		T210	1		T345	2
auto[1]	values[7]	values[3]	9	1			T96	1		T215	1		T248	1
auto[1]	values[7]	values[4]	3	1			T96	1		T267	1		T370	1
auto[1]	values[7]	values[5]	22	1			T266	4		T239	2		T322	2
auto[1]	values[7]	values[6]	9	1			T67	1		T227	2		T318	1
auto[1]	values[7]	values[7]	14	1			T215	1		T174	1		T211	1