Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	859	1			T32	24		T35	24		T95	4
all_values[1]	859	1			T32	24		T35	24		T95	4
all_values[2]	859	1			T32	24		T35	24		T95	4
all_values[3]	859	1			T32	24		T35	24		T95	4
all_values[4]	859	1			T32	24		T35	24		T95	4
all_values[5]	859	1			T32	24		T35	24		T95	4
all_values[6]	859	1			T32	24		T35	24		T95	4
all_values[7]	859	1			T32	24		T35	24		T95	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3695

1

T32

108

T35

108

T95

15

auto[1]

3177

1

T32

84

T35

84

T95

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2674

1

T32

81

T35

65

T95

17

auto[1]

4198

1

T32

111

T35

127

T95

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3835

1

T32

118

T35

100

T95

21

auto[1]

3037

1

T32

74

T35

92

T95

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	155	1			T32	5		T35	8		T95	1
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T32	1		T36	2		T37	1
all_values[0]	auto[0]	auto[1]	auto[0]	127	1			T32	10		T35	1		T95	2
all_values[0]	auto[0]	auto[1]	auto[1]	93	1			T32	2		T35	2		T36	2
all_values[0]	auto[1]	auto[0]	auto[1]	229	1			T32	4		T35	6		T95	1
all_values[0]	auto[1]	auto[1]	auto[1]	171	1			T32	2		T35	7		T36	4
all_values[1]	auto[0]	auto[0]	auto[0]	180	1			T32	6		T35	6		T36	4
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T32	4		T35	3		T36	1
all_values[1]	auto[0]	auto[1]	auto[0]	160	1			T32	2		T35	2		T36	3
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T32	3		T35	3		T95	1
all_values[1]	auto[1]	auto[0]	auto[1]	194	1			T32	6		T35	9		T95	1
all_values[1]	auto[1]	auto[1]	auto[1]	167	1			T32	3		T35	1		T95	2
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T32	9		T35	2		T95	1
all_values[2]	auto[0]	auto[0]	auto[1]	97	1			T32	3		T35	1		T36	3
all_values[2]	auto[0]	auto[1]	auto[0]	136	1			T35	4		T36	5		T156	6
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T32	2		T35	4		T95	1
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T32	8		T35	5		T36	4
all_values[2]	auto[1]	auto[1]	auto[1]	174	1			T32	2		T35	8		T95	2
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T32	2		T35	3		T36	5
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T32	3		T35	4		T95	1
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T32	6		T35	2		T95	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T32	3		T35	3		T36	3
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T32	5		T35	7		T95	2
all_values[3]	auto[1]	auto[1]	auto[1]	170	1			T32	5		T35	5		T36	4
all_values[4]	auto[0]	auto[0]	auto[0]	190	1			T32	5		T35	6		T95	1
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T35	3		T37	1		T156	2
all_values[4]	auto[0]	auto[1]	auto[0]	157	1			T32	8		T35	4		T95	1
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T32	2		T35	2		T95	1
all_values[4]	auto[1]	auto[0]	auto[1]	188	1			T32	6		T35	4		T95	1
all_values[4]	auto[1]	auto[1]	auto[1]	173	1			T32	3		T35	5		T36	5
all_values[5]	auto[0]	auto[0]	auto[0]	241	1			T32	7		T35	5		T95	2
all_values[5]	auto[0]	auto[1]	auto[0]	221	1			T32	8		T35	7		T36	2
all_values[5]	auto[1]	auto[0]	auto[1]	206	1			T32	6		T35	8		T95	2
all_values[5]	auto[1]	auto[1]	auto[1]	191	1			T32	3		T35	4		T36	4
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T32	1		T35	7		T95	1
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T32	10		T35	3		T36	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T32	2		T35	6		T95	3
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T32	2		T35	1		T36	2
all_values[6]	auto[1]	auto[0]	auto[1]	212	1			T32	5		T35	5		T36	8
all_values[6]	auto[1]	auto[1]	auto[1]	168	1			T32	4		T35	2		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T32	6		T35	1		T95	1
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T32	1		T35	3		T36	1
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T32	4		T35	1		T95	3
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T32	1		T35	3		T36	2
all_values[7]	auto[1]	auto[0]	auto[1]	223	1			T32	5		T35	9		T36	8
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T32	7		T35	7		T36	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal