Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1807

1

T4

6

T5

3

T15

4

auto[1]

1865

1

T4

2

T5

4

T7

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T7

1

T29

6

T73

5

auto[1]

1729

1

T4

8

T5

7

T15

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2958

1

T4

8

T5

7

T7

1

auto[1]

714

1

T29

1

T73

2

T58

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	734	1			T4	1		T5	2		T15	1
valid[1]	725	1			T4	1		T5	1		T7	1
valid[2]	739	1			T4	2		T5	1		T27	1
valid[3]	714	1			T4	1		T5	1		T15	2
valid[4]	760	1			T4	3		T5	2		T27	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	119	1			T29	1		T58	2		T75	1
auto[0]	auto[0]	valid[0]	auto[1]	176	1			T4	1		T5	1		T15	1
auto[0]	auto[0]	valid[1]	auto[0]	131	1			T29	1		T73	2		T74	2
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T15	1		T104	5		T109	3
auto[0]	auto[0]	valid[2]	auto[0]	115	1			T74	1		T107	1		T397	1
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T4	2		T5	1		T30	3
auto[0]	auto[0]	valid[3]	auto[0]	114	1			T29	1		T58	2		T74	2
auto[0]	auto[0]	valid[3]	auto[1]	164	1			T5	1		T15	2		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T73	1		T74	2		T125	2
auto[0]	auto[0]	valid[4]	auto[1]	184	1			T4	3		T27	1		T104	1
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T58	1		T49	1		T107	1
auto[0]	auto[1]	valid[0]	auto[1]	184	1			T5	1		T27	1		T104	2
auto[0]	auto[1]	valid[1]	auto[0]	131	1			T7	1		T29	1		T58	1
auto[0]	auto[1]	valid[1]	auto[1]	169	1			T4	1		T5	1		T104	1
auto[0]	auto[1]	valid[2]	auto[0]	137	1			T125	1		T49	3		T108	1
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T27	1		T30	1		T104	2
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T58	1		T74	1		T49	1
auto[0]	auto[1]	valid[3]	auto[1]	185	1			T4	1		T30	1		T104	1
auto[0]	auto[1]	valid[4]	auto[0]	129	1			T29	1		T58	1		T74	1
auto[0]	auto[1]	valid[4]	auto[1]	181	1			T5	2		T30	2		T104	1
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T75	2		T107	1		T67	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T58	2		T48	1		T395	1
auto[1]	auto[0]	valid[2]	auto[0]	87	1			T49	1		T47	1		T107	2
auto[1]	auto[0]	valid[3]	auto[0]	55	1			T73	1		T58	2		T74	1
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T29	1		T395	1		T397	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T74	1		T239	1		T156	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T58	1		T108	1		T96	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T58	3		T108	1		T106	1
auto[1]	auto[1]	valid[3]	auto[0]	77	1			T58	1		T74	1		T49	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T73	1		T58	1		T74	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal