Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49214

1

T6

7

T7

74

T25

7

auto[1]

18378

1

T4

8

T5

98

T7

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49740

1

T4

8

T5

98

T6

4

auto[1]

17852

1

T6

3

T7

30

T25

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34732	1			T4	8		T5	42		T6	4
others[1]	5658	1			T5	12		T7	5		T29	18
others[2]	5758	1			T5	7		T7	9		T25	1
others[3]	6433	1			T5	13		T7	8		T29	28
interest[1]	3754	1			T5	6		T7	5		T28	1
interest[4]	22686	1			T4	8		T5	29		T6	4
interest[64]	11257	1			T5	18		T6	3		T7	16

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15860	1			T6	2		T7	18		T25	5
auto[0]	auto[0]	others[1]	2666	1			T7	2		T29	16		T73	2
auto[0]	auto[0]	others[2]	2772	1			T7	8		T25	1		T29	22
auto[0]	auto[0]	others[3]	3030	1			T7	4		T29	18		T72	1
auto[0]	auto[0]	interest[1]	1740	1			T7	2		T29	12		T73	3
auto[0]	auto[0]	interest[4]	10365	1			T6	2		T7	12		T25	2
auto[0]	auto[0]	interest[64]	5294	1			T6	2		T7	10		T28	1
auto[0]	auto[1]	others[0]	9635	1			T4	8		T5	42		T7	2
auto[0]	auto[1]	others[1]	1534	1			T5	12		T104	23		T58	7
auto[0]	auto[1]	others[2]	1480	1			T5	7		T7	1		T104	21
auto[0]	auto[1]	others[3]	1721	1			T5	13		T104	31		T58	2
auto[0]	auto[1]	interest[1]	1012	1			T5	6		T7	1		T104	16
auto[0]	auto[1]	interest[4]	6352	1			T4	8		T5	29		T7	2
auto[0]	auto[1]	interest[64]	2996	1			T5	18		T104	39		T58	15
auto[1]	auto[0]	others[0]	9237	1			T6	2		T7	15		T25	1
auto[1]	auto[0]	others[1]	1458	1			T7	3		T29	2		T73	5
auto[1]	auto[0]	others[2]	1506	1			T28	2		T29	9		T73	3
auto[1]	auto[0]	others[3]	1682	1			T7	4		T29	10		T73	1
auto[1]	auto[0]	interest[1]	1002	1			T7	2		T28	1		T29	6
auto[1]	auto[0]	interest[4]	5969	1			T6	2		T7	11		T29	25
auto[1]	auto[0]	interest[64]	2967	1			T6	1		T7	6		T28	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal