Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2612242	1			T1	1		T2	1		T4	1
all_values[1]	2612242	1			T1	1		T2	1		T4	1
all_values[2]	2612242	1			T1	1		T2	1		T4	1
all_values[3]	2612242	1			T1	1		T2	1		T4	1
all_values[4]	2612242	1			T1	1		T2	1		T4	1
all_values[5]	2612242	1			T1	1		T2	1		T4	1
all_values[6]	2612242	1			T1	1		T2	1		T4	1
all_values[7]	2612242	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20464197

1

T1

8

T2

8

T4

8

auto[1]

433739

1

T14

89

T21

15

T34

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20871997

1

T1

8

T2

8

T4

8

auto[1]

25939

1

T14

51

T21

18

T34

31

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2549647	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	11645	1			T21	1		T34	1		T36	3
all_values[0]	auto[1]	auto[0]	50332	1			T14	11		T21	3		T34	1
all_values[0]	auto[1]	auto[1]	618	1			T14	3		T21	1		T34	3
all_values[1]	auto[0]	auto[0]	2532254	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	7832	1			T14	9		T21	1		T34	3
all_values[1]	auto[1]	auto[0]	71512	1			T14	4		T21	1		T34	6
all_values[1]	auto[1]	auto[1]	644	1			T14	3		T51	1		T77	4
all_values[2]	auto[0]	auto[0]	2545143	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	3137	1			T14	5		T21	3		T34	2
all_values[2]	auto[1]	auto[0]	63672	1			T14	2		T21	1		T36	6
all_values[2]	auto[1]	auto[1]	290	1			T14	4		T34	3		T36	2
all_values[3]	auto[0]	auto[0]	2587633	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	211	1			T14	3		T36	3		T97	4
all_values[3]	auto[1]	auto[0]	24230	1			T14	10		T21	1		T34	4
all_values[3]	auto[1]	auto[1]	168	1			T14	2		T21	1		T34	1
all_values[4]	auto[0]	auto[0]	2540764	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	181	1			T14	3		T21	3		T34	3
all_values[4]	auto[1]	auto[0]	71122	1			T14	13		T34	1		T36	1
all_values[4]	auto[1]	auto[1]	175	1			T34	3		T51	6		T77	5
all_values[5]	auto[0]	auto[0]	2563490	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	164	1			T14	2		T34	2		T36	1
all_values[5]	auto[1]	auto[0]	48424	1			T14	12		T21	3		T34	5
all_values[5]	auto[1]	auto[1]	164	1			T14	6		T21	2		T34	1
all_values[6]	auto[0]	auto[0]	2561374	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	158	1			T14	3		T21	3		T34	1
all_values[6]	auto[1]	auto[0]	50516	1			T14	10		T34	3		T36	3
all_values[6]	auto[1]	auto[1]	194	1			T14	3		T21	1		T34	5
all_values[7]	auto[0]	auto[0]	2560383	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	181	1			T14	4		T21	2		T34	2
all_values[7]	auto[1]	auto[0]	51501	1			T14	5		T21	1		T34	6
all_values[7]	auto[1]	auto[1]	177	1			T14	1		T34	1		T36	1