Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total tests in report: 1150
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.14 62.14 92.72 92.72 78.85 78.85 64.27 64.27 31.11 31.11 89.26 89.26 71.71 71.71 7.03 7.03 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.1373253550
70.24 8.10 94.31 1.59 83.73 4.88 64.27 0.00 60.00 28.89 91.46 2.20 76.86 5.14 21.04 14.01 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3373419313
77.13 6.89 97.04 2.73 89.20 5.47 67.03 2.76 80.00 20.00 95.25 3.79 84.43 7.57 26.98 5.94 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3830130800
80.83 3.70 97.28 0.23 90.01 0.81 85.33 18.31 84.44 4.44 95.62 0.37 84.43 0.00 28.71 1.73 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1907320665
83.90 3.07 97.72 0.45 91.08 1.07 87.40 2.07 86.67 2.22 96.11 0.49 84.57 0.14 43.76 15.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1937167771
86.01 2.10 97.81 0.08 91.13 0.05 87.40 0.00 91.11 4.44 96.21 0.10 84.57 0.00 53.81 10.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1485403736
87.58 1.58 97.81 0.00 91.30 0.17 87.80 0.39 91.11 0.00 96.24 0.03 93.29 8.71 55.54 1.73 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.480545346
88.71 1.12 97.81 0.00 91.30 0.00 87.80 0.00 91.11 0.00 96.24 0.00 93.29 0.00 63.42 7.87 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3363291945
89.73 1.02 97.95 0.14 91.60 0.30 87.80 0.00 93.33 2.22 96.43 0.19 93.43 0.14 67.57 4.16 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2341794895
90.49 0.76 98.06 0.11 91.96 0.36 88.78 0.98 93.33 0.00 96.65 0.22 93.43 0.00 71.24 3.66 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1574027145
91.17 0.68 98.07 0.01 91.96 0.00 93.50 4.72 93.33 0.00 96.65 0.00 93.43 0.00 71.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3298303980
91.73 0.56 98.09 0.03 92.00 0.04 93.50 0.00 93.33 0.00 96.72 0.07 93.43 0.00 75.05 3.81 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3356226468
92.25 0.52 98.28 0.19 92.80 0.81 95.28 1.77 93.33 0.00 97.04 0.32 94.00 0.57 75.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3485562846
92.71 0.45 98.28 0.00 92.80 0.00 95.28 0.00 93.33 0.00 97.04 0.00 94.00 0.00 78.22 3.17 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1164614716
93.09 0.39 98.29 0.01 92.84 0.04 97.34 2.07 93.33 0.00 97.06 0.02 94.29 0.29 78.51 0.30 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2415338243
93.46 0.36 98.29 0.00 92.85 0.01 97.34 0.00 93.33 0.00 97.07 0.02 94.29 0.00 81.04 2.52 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.4148981421
93.77 0.31 98.29 0.00 92.85 0.00 97.34 0.00 93.33 0.00 97.07 0.00 94.29 0.00 83.22 2.18 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.534923854
94.04 0.27 98.29 0.00 92.89 0.04 98.03 0.69 93.33 0.00 97.07 0.00 94.29 0.00 84.41 1.19 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3855552347
94.29 0.25 98.29 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.07 0.00 94.29 0.00 86.14 1.73 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.675429582
94.52 0.23 98.29 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.07 0.00 94.43 0.14 87.57 1.44 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3766670613
94.71 0.19 98.29 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.07 0.00 94.43 0.00 88.91 1.34 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1238003856
94.86 0.16 98.29 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.07 0.00 94.43 0.00 90.00 1.09 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2356830421
95.01 0.14 98.29 0.00 92.89 0.00 98.03 0.00 93.33 0.00 97.07 0.00 95.43 1.00 90.00 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3685983555
95.15 0.14 98.30 0.01 92.97 0.07 98.03 0.00 93.33 0.00 97.09 0.02 95.43 0.00 90.89 0.89 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1382109982
95.28 0.13 98.30 0.00 93.71 0.75 98.03 0.00 93.33 0.00 97.09 0.00 95.43 0.00 91.04 0.15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3204562087
95.40 0.13 98.30 0.00 93.71 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.43 0.00 91.93 0.89 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2661967035
95.51 0.11 98.30 0.00 93.71 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.43 0.00 92.67 0.74 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.972959926
95.61 0.10 98.30 0.00 93.71 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.43 0.00 93.37 0.69 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.631505907
95.70 0.09 98.30 0.00 93.71 0.00 98.03 0.00 93.33 0.00 97.09 0.00 95.43 0.00 94.01 0.64 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2034771930
95.79 0.09 98.35 0.06 93.81 0.10 98.43 0.39 93.33 0.00 97.18 0.08 95.43 0.00 94.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3854527330
95.87 0.08 98.35 0.00 93.82 0.01 98.43 0.00 93.33 0.00 97.18 0.00 95.43 0.00 94.55 0.54 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1023643271
95.94 0.06 98.38 0.03 93.85 0.02 98.43 0.00 93.33 0.00 97.23 0.05 95.43 0.00 94.90 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.1199149890
95.99 0.06 98.38 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 95.30 0.40 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.179537502
96.05 0.06 98.38 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 95.69 0.40 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2983662856
96.10 0.05 98.38 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.04 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4152997381
96.14 0.04 98.38 0.00 93.85 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.34 0.30 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.1535613960
96.18 0.04 98.41 0.03 93.89 0.04 98.62 0.20 93.33 0.00 97.23 0.00 95.43 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3203791435
96.21 0.04 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.58 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2175061753
96.25 0.04 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.83 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.477627458
96.28 0.04 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.08 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.3361356125
96.32 0.04 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.33 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2109471502
96.35 0.03 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.52 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.58219678
96.38 0.03 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.72 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2912414342
96.40 0.03 98.41 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.92 0.20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.982160447
96.43 0.03 98.41 0.00 93.94 0.05 98.62 0.00 93.33 0.00 97.26 0.03 95.43 0.00 98.02 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.2386803197
96.45 0.02 98.41 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.312611299
96.47 0.02 98.41 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.32 0.15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2405639640
96.49 0.02 98.42 0.01 93.94 0.00 98.62 0.00 93.33 0.00 97.28 0.02 95.43 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1228505720
96.51 0.02 98.42 0.00 94.01 0.07 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.47 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1292627404
96.52 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1125152151
96.54 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3242854913
96.55 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.127076491
96.56 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3808145920
96.58 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.96 0.10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3156530811
96.59 0.01 98.42 0.00 94.02 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1076265711
96.59 0.01 98.42 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2835433462
96.60 0.01 98.42 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2949747614
96.61 0.01 98.42 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3478141983
96.62 0.01 98.42 0.00 94.02 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.2970555870
96.62 0.01 98.44 0.02 94.05 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1609593664
96.63 0.01 98.44 0.00 94.07 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1457526333
96.63 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3807413881

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1565093172
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3990037711
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1060604258
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2343792051
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2172152146
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.4029676874
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2011209482
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.626588526
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1638746567
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3591208523
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.774932002
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1384055665
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4143038226
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1838806425
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.745736669
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.523272910
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2295227013
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2597285218
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2709067506
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.575378286
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.106060245
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3430109268
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/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1219186749
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1270957081
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.815211513
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1024520589
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1408189522
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.3368870478
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2182056899
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.179320717
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3038624382
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2567421084
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2066309038
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.4115468153
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2749495621
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3652269084
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.797270453
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2850213463
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1904340775
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1932196640
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2876884532
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.439290536
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3424618223
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3261929659
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1328732426
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.274992501
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3604895560
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4280553235
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.2031118937
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1231897089
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.923465557
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2259908422
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2185746884
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3914360124
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.1512436687
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1969994096
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.629261367
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2550852746
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.4164640446
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2166720983
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.2565310881
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.755077210
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2438233611
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2158220410
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1572550121
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.489227146
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.4056288878
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.70717419
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3950852990
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2963426824
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2334617418
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2922324323
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1977846250
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1801522702
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2111101259
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3678979261
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3994610173
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.265447614
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2563527520
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3634743428
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1302469726
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3161015375
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.292570885
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1608185124
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1884918013
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.334097018
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3339134418
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1149400266



Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1609593664 Aug 27 07:40:56 PM UTC 24 Aug 27 07:40:58 PM UTC 24 14143814 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3298303980 Aug 27 07:41:00 PM UTC 24 Aug 27 07:41:02 PM UTC 24 18057956 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3854527330 Aug 27 07:41:00 PM UTC 24 Aug 27 07:41:02 PM UTC 24 18742399 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.898020102 Aug 27 07:41:03 PM UTC 24 Aug 27 07:41:06 PM UTC 24 153287496 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3855552347 Aug 27 07:41:03 PM UTC 24 Aug 27 07:41:08 PM UTC 24 655149506 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.176787280 Aug 27 07:41:06 PM UTC 24 Aug 27 07:41:09 PM UTC 24 73250934 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3312387436 Aug 27 07:41:08 PM UTC 24 Aug 27 07:41:14 PM UTC 24 405574164 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3919216465 Aug 27 07:41:09 PM UTC 24 Aug 27 07:41:14 PM UTC 24 149781061 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.1373253550 Aug 27 07:41:08 PM UTC 24 Aug 27 07:41:14 PM UTC 24 286055968 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.3338872 Aug 27 07:41:03 PM UTC 24 Aug 27 07:41:16 PM UTC 24 667837218 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3672569374 Aug 27 07:41:09 PM UTC 24 Aug 27 07:41:19 PM UTC 24 985082513 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3866625768 Aug 27 07:41:08 PM UTC 24 Aug 27 07:41:21 PM UTC 24 4589412602 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2939712187 Aug 27 07:41:15 PM UTC 24 Aug 27 07:41:23 PM UTC 24 282238407 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3203791435 Aug 27 07:41:21 PM UTC 24 Aug 27 07:41:23 PM UTC 24 47669100 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2947119292 Aug 27 07:41:21 PM UTC 24 Aug 27 07:41:23 PM UTC 24 184361824 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2415338243 Aug 27 07:41:21 PM UTC 24 Aug 27 07:41:23 PM UTC 24 158427430 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.2908584091 Aug 27 07:41:22 PM UTC 24 Aug 27 07:41:24 PM UTC 24 34287289 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.950034029 Aug 27 07:41:22 PM UTC 24 Aug 27 07:41:25 PM UTC 24 16474725 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.311042473 Aug 27 07:41:24 PM UTC 24 Aug 27 07:41:26 PM UTC 24 56938691 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.706197591 Aug 27 07:41:24 PM UTC 24 Aug 27 07:41:26 PM UTC 24 27939537 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3830130800 Aug 27 07:41:24 PM UTC 24 Aug 27 07:41:30 PM UTC 24 598442727 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.3078297227 Aug 27 07:41:27 PM UTC 24 Aug 27 07:41:31 PM UTC 24 291005489 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1753918212 Aug 27 07:41:25 PM UTC 24 Aug 27 07:41:31 PM UTC 24 379927253 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2498485468 Aug 27 07:41:08 PM UTC 24 Aug 27 07:41:32 PM UTC 24 1687833412 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1574027145 Aug 27 07:41:27 PM UTC 24 Aug 27 07:41:34 PM UTC 24 207891973 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1907320665 Aug 27 07:41:25 PM UTC 24 Aug 27 07:41:34 PM UTC 24 464880631 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.774977248 Aug 27 07:41:31 PM UTC 24 Aug 27 07:41:36 PM UTC 24 117958516 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1114725235 Aug 27 07:41:09 PM UTC 24 Aug 27 07:41:36 PM UTC 24 5869795420 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3485562846 Aug 27 07:41:32 PM UTC 24 Aug 27 07:41:37 PM UTC 24 345444150 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1228505720 Aug 27 07:41:25 PM UTC 24 Aug 27 07:41:37 PM UTC 24 377549623 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.277484363 Aug 27 07:41:36 PM UTC 24 Aug 27 07:41:38 PM UTC 24 187987560 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.644044866 Aug 27 07:41:36 PM UTC 24 Aug 27 07:41:38 PM UTC 24 55255779 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.293802030 Aug 27 07:41:37 PM UTC 24 Aug 27 07:41:39 PM UTC 24 82911691 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2679768049 Aug 27 07:41:37 PM UTC 24 Aug 27 07:41:39 PM UTC 24 18575173 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1171262350 Aug 27 07:41:39 PM UTC 24 Aug 27 07:41:41 PM UTC 24 29539976 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.2285541922 Aug 27 07:41:38 PM UTC 24 Aug 27 07:41:41 PM UTC 24 159264946 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3476799225 Aug 27 07:41:24 PM UTC 24 Aug 27 07:41:42 PM UTC 24 4295577026 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2844095106 Aug 27 07:41:27 PM UTC 24 Aug 27 07:41:43 PM UTC 24 491167070 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.986237619 Aug 27 07:41:40 PM UTC 24 Aug 27 07:41:44 PM UTC 24 60311818 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2467979818 Aug 27 07:41:40 PM UTC 24 Aug 27 07:41:44 PM UTC 24 58659980 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4022487040 Aug 27 07:41:42 PM UTC 24 Aug 27 07:41:46 PM UTC 24 428551072 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.705158204 Aug 27 07:41:42 PM UTC 24 Aug 27 07:41:46 PM UTC 24 55258066 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1477401590 Aug 27 07:41:40 PM UTC 24 Aug 27 07:41:46 PM UTC 24 722844855 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2607323261 Aug 27 07:41:47 PM UTC 24 Aug 27 07:41:49 PM UTC 24 11508913 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.203722548 Aug 27 07:41:40 PM UTC 24 Aug 27 07:41:49 PM UTC 24 302437628 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2230589261 Aug 27 07:41:47 PM UTC 24 Aug 27 07:41:50 PM UTC 24 153783567 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.137012188 Aug 27 07:41:47 PM UTC 24 Aug 27 07:41:50 PM UTC 24 60083925 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3293008230 Aug 27 07:41:38 PM UTC 24 Aug 27 07:41:51 PM UTC 24 10303177016 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.835326836 Aug 27 07:41:50 PM UTC 24 Aug 27 07:41:52 PM UTC 24 53856777 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.701899961 Aug 27 07:41:42 PM UTC 24 Aug 27 07:41:52 PM UTC 24 1363091674 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.3320449442 Aug 27 07:41:50 PM UTC 24 Aug 27 07:41:53 PM UTC 24 93249631 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3013022443 Aug 27 07:41:39 PM UTC 24 Aug 27 07:41:54 PM UTC 24 1050844807 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1544989984 Aug 27 07:41:43 PM UTC 24 Aug 27 07:41:54 PM UTC 24 4616846063 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3986932319 Aug 27 07:41:52 PM UTC 24 Aug 27 07:41:55 PM UTC 24 34355556 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1064434654 Aug 27 07:41:54 PM UTC 24 Aug 27 07:41:57 PM UTC 24 50478274 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.1218104338 Aug 27 07:41:42 PM UTC 24 Aug 27 07:41:57 PM UTC 24 462445913 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.1856295379 Aug 27 07:41:54 PM UTC 24 Aug 27 07:41:58 PM UTC 24 64407679 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2572435033 Aug 27 07:41:51 PM UTC 24 Aug 27 07:41:59 PM UTC 24 4139262071 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.1799354636 Aug 27 07:41:55 PM UTC 24 Aug 27 07:41:59 PM UTC 24 62448301 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.435217248 Aug 27 07:42:00 PM UTC 24 Aug 27 07:42:03 PM UTC 24 176990078 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.883191512 Aug 27 07:41:51 PM UTC 24 Aug 27 07:42:03 PM UTC 24 715356338 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.3846901876 Aug 27 07:41:55 PM UTC 24 Aug 27 07:42:04 PM UTC 24 816499448 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2169740269 Aug 27 07:42:04 PM UTC 24 Aug 27 07:42:06 PM UTC 24 12651708 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1389045884 Aug 27 07:41:56 PM UTC 24 Aug 27 07:42:06 PM UTC 24 2313866021 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1974208476 Aug 27 07:42:04 PM UTC 24 Aug 27 07:42:06 PM UTC 24 143022665 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2788118625 Aug 27 07:41:56 PM UTC 24 Aug 27 07:42:06 PM UTC 24 956935671 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.88683295 Aug 27 07:41:54 PM UTC 24 Aug 27 07:42:06 PM UTC 24 1918591910 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3647425747 Aug 27 07:42:05 PM UTC 24 Aug 27 07:42:07 PM UTC 24 41219945 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1534038394 Aug 27 07:42:05 PM UTC 24 Aug 27 07:42:08 PM UTC 24 26679474 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.715852588 Aug 27 07:41:54 PM UTC 24 Aug 27 07:42:08 PM UTC 24 5589978750 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.1900159447 Aug 27 07:42:07 PM UTC 24 Aug 27 07:42:10 PM UTC 24 12627019 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.4278252896 Aug 27 07:42:07 PM UTC 24 Aug 27 07:42:10 PM UTC 24 127750554 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3181321902 Aug 27 07:41:59 PM UTC 24 Aug 27 07:42:14 PM UTC 24 15498543744 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.351947183 Aug 27 07:42:11 PM UTC 24 Aug 27 07:42:17 PM UTC 24 226026668 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3426702789 Aug 27 07:42:07 PM UTC 24 Aug 27 07:42:18 PM UTC 24 247038263 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1164614716 Aug 27 07:41:15 PM UTC 24 Aug 27 07:42:19 PM UTC 24 15794778311 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1110202635 Aug 27 07:42:08 PM UTC 24 Aug 27 07:42:20 PM UTC 24 1225092284 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.4091009038 Aug 27 07:42:08 PM UTC 24 Aug 27 07:42:21 PM UTC 24 8679964181 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3550365770 Aug 27 07:41:59 PM UTC 24 Aug 27 07:42:21 PM UTC 24 4727741511 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.4214704672 Aug 27 07:42:10 PM UTC 24 Aug 27 07:42:22 PM UTC 24 6020792634 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2687586085 Aug 27 07:42:14 PM UTC 24 Aug 27 07:42:22 PM UTC 24 916036265 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3716840084 Aug 27 07:42:20 PM UTC 24 Aug 27 07:42:22 PM UTC 24 178071235 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3928013007 Aug 27 07:42:21 PM UTC 24 Aug 27 07:42:23 PM UTC 24 15725649 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.2399784084 Aug 27 07:42:21 PM UTC 24 Aug 27 07:42:24 PM UTC 24 120551901 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3431605735 Aug 27 07:42:22 PM UTC 24 Aug 27 07:42:24 PM UTC 24 24972676 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.164714682 Aug 27 07:42:22 PM UTC 24 Aug 27 07:42:25 PM UTC 24 15252814 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2503827214 Aug 27 07:42:11 PM UTC 24 Aug 27 07:42:26 PM UTC 24 560874116 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4033677222 Aug 27 07:42:19 PM UTC 24 Aug 27 07:42:26 PM UTC 24 1427329159 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3664288082 Aug 27 07:42:25 PM UTC 24 Aug 27 07:42:27 PM UTC 24 107594645 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2946136867 Aug 27 07:42:25 PM UTC 24 Aug 27 07:42:27 PM UTC 24 669792815 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.3693235278 Aug 27 07:41:45 PM UTC 24 Aug 27 07:42:28 PM UTC 24 62697540256 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3618333915 Aug 27 07:42:25 PM UTC 24 Aug 27 07:42:30 PM UTC 24 164767187 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3373419313 Aug 27 07:41:45 PM UTC 24 Aug 27 07:42:30 PM UTC 24 1648364767 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3526376356 Aug 27 07:42:25 PM UTC 24 Aug 27 07:42:30 PM UTC 24 2098981104 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.3361356125 Aug 27 07:42:07 PM UTC 24 Aug 27 07:42:31 PM UTC 24 3328632223 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1548043137 Aug 27 07:42:32 PM UTC 24 Aug 27 07:42:34 PM UTC 24 22277438 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1089761535 Aug 27 07:41:58 PM UTC 24 Aug 27 07:42:35 PM UTC 24 2007390358 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.57472998 Aug 27 07:42:26 PM UTC 24 Aug 27 07:42:35 PM UTC 24 360938740 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1745020540 Aug 27 07:42:10 PM UTC 24 Aug 27 07:42:36 PM UTC 24 5337805416 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.2661691327 Aug 27 07:42:35 PM UTC 24 Aug 27 07:42:37 PM UTC 24 19229248 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1187334154 Aug 27 07:42:28 PM UTC 24 Aug 27 07:42:39 PM UTC 24 458894756 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2567421084 Aug 27 07:42:36 PM UTC 24 Aug 27 07:42:39 PM UTC 24 57012010 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1270957081 Aug 27 07:42:36 PM UTC 24 Aug 27 07:42:39 PM UTC 24 99249105 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1479672262 Aug 27 07:42:24 PM UTC 24 Aug 27 07:42:39 PM UTC 24 6326967720 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.179320717 Aug 27 07:42:36 PM UTC 24 Aug 27 07:42:39 PM UTC 24 4250971174 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.770618154 Aug 27 07:42:29 PM UTC 24 Aug 27 07:42:39 PM UTC 24 3448245598 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2341794895 Aug 27 07:41:33 PM UTC 24 Aug 27 07:42:43 PM UTC 24 18980394316 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1024520589 Aug 27 07:42:38 PM UTC 24 Aug 27 07:42:43 PM UTC 24 779004936 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1892168692 Aug 27 07:42:07 PM UTC 24 Aug 27 07:42:44 PM UTC 24 13777715464 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3038624382 Aug 27 07:42:38 PM UTC 24 Aug 27 07:42:44 PM UTC 24 446885197 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2843758752 Aug 27 07:42:40 PM UTC 24 Aug 27 07:42:45 PM UTC 24 225289636 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2066309038 Aug 27 07:42:40 PM UTC 24 Aug 27 07:42:46 PM UTC 24 635341973 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2285013736 Aug 27 07:42:39 PM UTC 24 Aug 27 07:42:47 PM UTC 24 1018891793 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2394488727 Aug 27 07:42:46 PM UTC 24 Aug 27 07:42:48 PM UTC 24 17080987 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1102453287 Aug 27 07:42:28 PM UTC 24 Aug 27 07:42:48 PM UTC 24 11833797165 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1219186749 Aug 27 07:42:39 PM UTC 24 Aug 27 07:42:49 PM UTC 24 732198666 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3652269084 Aug 27 07:42:47 PM UTC 24 Aug 27 07:42:49 PM UTC 24 16794766 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1485403736 Aug 27 07:41:33 PM UTC 24 Aug 27 07:42:49 PM UTC 24 7148788803 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3424618223 Aug 27 07:42:47 PM UTC 24 Aug 27 07:42:50 PM UTC 24 114238616 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1408189522 Aug 27 07:42:44 PM UTC 24 Aug 27 07:42:50 PM UTC 24 179440262 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3604895560 Aug 27 07:42:49 PM UTC 24 Aug 27 07:42:51 PM UTC 24 20741564 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.3726714491 Aug 27 07:42:44 PM UTC 24 Aug 27 07:42:52 PM UTC 24 934368770 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.963948015 Aug 27 07:42:24 PM UTC 24 Aug 27 07:42:52 PM UTC 24 8955849571 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.2031118937 Aug 27 07:42:51 PM UTC 24 Aug 27 07:42:53 PM UTC 24 34188991 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.3251936144 Aug 27 07:42:28 PM UTC 24 Aug 27 07:42:53 PM UTC 24 8444383878 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1231897089 Aug 27 07:42:51 PM UTC 24 Aug 27 07:42:53 PM UTC 24 574132321 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2318028989 Aug 27 07:42:00 PM UTC 24 Aug 27 07:42:54 PM UTC 24 87926783586 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3261929659 Aug 27 07:42:51 PM UTC 24 Aug 27 07:42:57 PM UTC 24 3944413388 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.923465557 Aug 27 07:42:53 PM UTC 24 Aug 27 07:42:57 PM UTC 24 318601497 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1328732426 Aug 27 07:42:51 PM UTC 24 Aug 27 07:42:58 PM UTC 24 1203506349 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.274992501 Aug 27 07:42:54 PM UTC 24 Aug 27 07:43:00 PM UTC 24 67383201 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.4115468153 Aug 27 07:42:59 PM UTC 24 Aug 27 07:43:01 PM UTC 24 14589042 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2749495621 Aug 27 07:42:53 PM UTC 24 Aug 27 07:43:03 PM UTC 24 1604841528 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3914360124 Aug 27 07:43:01 PM UTC 24 Aug 27 07:43:03 PM UTC 24 35967583 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.2565310881 Aug 27 07:43:02 PM UTC 24 Aug 27 07:43:05 PM UTC 24 183938684 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4280553235 Aug 27 07:42:49 PM UTC 24 Aug 27 07:43:05 PM UTC 24 1951212522 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2876884532 Aug 27 07:42:51 PM UTC 24 Aug 27 07:43:05 PM UTC 24 5838859195 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.815211513 Aug 27 07:42:38 PM UTC 24 Aug 27 07:43:06 PM UTC 24 6571546880 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3950852990 Aug 27 07:43:04 PM UTC 24 Aug 27 07:43:06 PM UTC 24 42784872 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3614102689 Aug 27 07:42:28 PM UTC 24 Aug 27 07:43:08 PM UTC 24 41483257377 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.70717419 Aug 27 07:43:06 PM UTC 24 Aug 27 07:43:08 PM UTC 24 18359718 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.4056288878 Aug 27 07:43:04 PM UTC 24 Aug 27 07:43:08 PM UTC 24 1943880078 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2182056899 Aug 27 07:42:36 PM UTC 24 Aug 27 07:43:12 PM UTC 24 8488886779 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1932196640 Aug 27 07:42:53 PM UTC 24 Aug 27 07:43:13 PM UTC 24 3407711544 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1904340775 Aug 27 07:42:58 PM UTC 24 Aug 27 07:43:13 PM UTC 24 515605021 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.4164640446 Aug 27 07:43:07 PM UTC 24 Aug 27 07:43:14 PM UTC 24 187169103 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.629261367 Aug 27 07:43:10 PM UTC 24 Aug 27 07:43:16 PM UTC 24 848465064 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2438233611 Aug 27 07:43:06 PM UTC 24 Aug 27 07:43:17 PM UTC 24 508016748 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2185746884 Aug 27 07:43:10 PM UTC 24 Aug 27 07:43:17 PM UTC 24 1220913623 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2259908422 Aug 27 07:43:17 PM UTC 24 Aug 27 07:43:18 PM UTC 24 122748855 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1977846250 Aug 27 07:43:18 PM UTC 24 Aug 27 07:43:20 PM UTC 24 70654557 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2034771930 Aug 27 07:42:18 PM UTC 24 Aug 27 07:43:20 PM UTC 24 68067776219 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3634743428 Aug 27 07:43:18 PM UTC 24 Aug 27 07:43:20 PM UTC 24 15482076 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2158220410 Aug 27 07:43:13 PM UTC 24 Aug 27 07:43:21 PM UTC 24 1136093780 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.4103317105 Aug 27 07:42:40 PM UTC 24 Aug 27 07:43:23 PM UTC 24 25347072257 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.3368870478 Aug 27 07:42:45 PM UTC 24 Aug 27 07:43:26 PM UTC 24 8521252635 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3339134418 Aug 27 07:43:21 PM UTC 24 Aug 27 07:43:23 PM UTC 24 40608322 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.334097018 Aug 27 07:43:21 PM UTC 24 Aug 27 07:43:24 PM UTC 24 81253870 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2963426824 Aug 27 07:43:08 PM UTC 24 Aug 27 07:43:26 PM UTC 24 3624405321 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.439290536 Aug 27 07:42:52 PM UTC 24 Aug 27 07:43:28 PM UTC 24 3392614666 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3161015375 Aug 27 07:43:22 PM UTC 24 Aug 27 07:43:30 PM UTC 24 1087424422 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.755077210 Aug 27 07:43:06 PM UTC 24 Aug 27 07:43:31 PM UTC 24 2912976240 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1149400266 Aug 27 07:43:24 PM UTC 24 Aug 27 07:43:31 PM UTC 24 399137159 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3017220896 Aug 27 07:44:08 PM UTC 24 Aug 27 07:44:45 PM UTC 24 14859666161 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3678979261 Aug 27 07:43:27 PM UTC 24 Aug 27 07:43:31 PM UTC 24 106065256 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1884918013 Aug 27 07:43:19 PM UTC 24 Aug 27 07:43:33 PM UTC 24 12391328022 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1023643271 Aug 27 07:42:29 PM UTC 24 Aug 27 07:43:35 PM UTC 24 2463122702 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2334617418 Aug 27 07:43:35 PM UTC 24 Aug 27 07:43:37 PM UTC 24 91221012 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.489227146 Aug 27 07:43:04 PM UTC 24 Aug 27 07:43:38 PM UTC 24 5276837895 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.489998752 Aug 27 07:41:32 PM UTC 24 Aug 27 07:43:39 PM UTC 24 156815940525 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3384943084 Aug 27 07:42:17 PM UTC 24 Aug 27 07:43:39 PM UTC 24 8876452742 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1306307187 Aug 27 07:43:38 PM UTC 24 Aug 27 07:43:41 PM UTC 24 31799620 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.1593482398 Aug 27 07:43:38 PM UTC 24 Aug 27 07:43:41 PM UTC 24 14085786 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2922324323 Aug 27 07:43:27 PM UTC 24 Aug 27 07:43:41 PM UTC 24 3487712913 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2563527520 Aug 27 07:43:24 PM UTC 24 Aug 27 07:43:42 PM UTC 24 4330979736 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1972373364 Aug 27 07:43:42 PM UTC 24 Aug 27 07:43:44 PM UTC 24 26525982 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.3255671386 Aug 27 07:43:42 PM UTC 24 Aug 27 07:43:45 PM UTC 24 119897929 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3108387603 Aug 27 07:43:39 PM UTC 24 Aug 27 07:43:46 PM UTC 24 2451118610 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1937167771 Aug 27 07:42:58 PM UTC 24 Aug 27 07:43:47 PM UTC 24 10098809013 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.292570885 Aug 27 07:43:31 PM UTC 24 Aug 27 07:43:47 PM UTC 24 4287268917 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2610226141 Aug 27 07:43:43 PM UTC 24 Aug 27 07:43:47 PM UTC 24 952001240 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3724165576 Aug 27 07:43:46 PM UTC 24 Aug 27 07:43:50 PM UTC 24 141558372 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3835564087 Aug 27 07:43:41 PM UTC 24 Aug 27 07:43:50 PM UTC 24 1026578154 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2042504029 Aug 27 07:43:42 PM UTC 24 Aug 27 07:43:52 PM UTC 24 296696190 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.265447614 Aug 27 07:43:24 PM UTC 24 Aug 27 07:43:52 PM UTC 24 2267901484 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1608185124 Aug 27 07:43:21 PM UTC 24 Aug 27 07:43:53 PM UTC 24 54571512878 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1302469726 Aug 27 07:43:23 PM UTC 24 Aug 27 07:43:55 PM UTC 24 7207945516 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1993930006 Aug 27 07:43:53 PM UTC 24 Aug 27 07:43:55 PM UTC 24 22000922 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.2836676704 Aug 27 07:43:53 PM UTC 24 Aug 27 07:43:55 PM UTC 24 12176892 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.978912019 Aug 27 07:43:54 PM UTC 24 Aug 27 07:43:57 PM UTC 24 123713940 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.404958228 Aug 27 07:43:47 PM UTC 24 Aug 27 07:43:58 PM UTC 24 1865003954 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2550852746 Aug 27 07:43:10 PM UTC 24 Aug 27 07:43:58 PM UTC 24 4748051553 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1367682145 Aug 27 07:43:56 PM UTC 24 Aug 27 07:43:59 PM UTC 24 24662035 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3399543651 Aug 27 07:43:56 PM UTC 24 Aug 27 07:43:59 PM UTC 24 131029365 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.2510331898 Aug 27 07:43:47 PM UTC 24 Aug 27 07:44:02 PM UTC 24 1040666100 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.3414457490 Aug 27 07:43:56 PM UTC 24 Aug 27 07:44:05 PM UTC 24 635521133 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3824785145 Aug 27 07:43:46 PM UTC 24 Aug 27 07:44:05 PM UTC 24 24376915529 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2406815826 Aug 27 07:43:44 PM UTC 24 Aug 27 07:44:06 PM UTC 24 9014947276 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2878098123 Aug 27 07:44:00 PM UTC 24 Aug 27 07:44:06 PM UTC 24 815086335 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2332274443 Aug 27 07:44:05 PM UTC 24 Aug 27 07:44:07 PM UTC 24 16404885 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.2327845346 Aug 27 07:43:59 PM UTC 24 Aug 27 07:44:08 PM UTC 24 707670669 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3623611325 Aug 27 07:43:58 PM UTC 24 Aug 27 07:44:09 PM UTC 24 7511669492 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.684825133 Aug 27 07:43:58 PM UTC 24 Aug 27 07:44:11 PM UTC 24 1543876995 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1506141530 Aug 27 07:44:10 PM UTC 24 Aug 27 07:44:12 PM UTC 24 82483508 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.2568921653 Aug 27 07:44:10 PM UTC 24 Aug 27 07:44:13 PM UTC 24 18318715 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3094946739 Aug 27 07:44:12 PM UTC 24 Aug 27 07:44:15 PM UTC 24 17096092 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2645808911 Aug 27 07:43:59 PM UTC 24 Aug 27 07:44:16 PM UTC 24 5035036238 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3994610173 Aug 27 07:43:29 PM UTC 24 Aug 27 07:44:17 PM UTC 24 1832555667 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1113918605 Aug 27 07:44:07 PM UTC 24 Aug 27 07:44:18 PM UTC 24 1729807648 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4049433605 Aug 27 07:44:16 PM UTC 24 Aug 27 07:44:18 PM UTC 24 31321574 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.2754993437 Aug 27 07:44:17 PM UTC 24 Aug 27 07:44:19 PM UTC 24 158399599 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1096658817 Aug 27 07:43:55 PM UTC 24 Aug 27 07:44:23 PM UTC 24 5896754939 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1572550121 Aug 27 07:43:15 PM UTC 24 Aug 27 07:44:23 PM UTC 24 2284200451 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2166720983 Aug 27 07:43:07 PM UTC 24 Aug 27 07:44:26 PM UTC 24 8164942549 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.1328285546 Aug 27 07:44:42 PM UTC 24 Aug 27 07:44:48 PM UTC 24 488434042 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2733261056 Aug 27 07:43:59 PM UTC 24 Aug 27 07:44:26 PM UTC 24 12032257160 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.1744633527 Aug 27 07:44:20 PM UTC 24 Aug 27 07:44:27 PM UTC 24 998935099 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1732236811 Aug 27 07:44:18 PM UTC 24 Aug 27 07:44:27 PM UTC 24 1547070722 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2068433707 Aug 27 07:44:03 PM UTC 24 Aug 27 07:44:28 PM UTC 24 14296987880 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.534923854 Aug 27 07:42:31 PM UTC 24 Aug 27 07:44:28 PM UTC 24 66689511321 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2661967035 Aug 27 07:41:34 PM UTC 24 Aug 27 07:44:31 PM UTC 24 34212613049 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2850213463 Aug 27 07:42:57 PM UTC 24 Aug 27 07:44:31 PM UTC 24 21414022584 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.166361000 Aug 27 07:44:27 PM UTC 24 Aug 27 07:44:33 PM UTC 24 767626982 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.2975509083 Aug 27 07:44:33 PM UTC 24 Aug 27 07:44:35 PM UTC 24 12342378 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.1465512152 Aug 27 07:44:24 PM UTC 24 Aug 27 07:44:35 PM UTC 24 10024238648 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3086966920 Aug 27 07:44:34 PM UTC 24 Aug 27 07:44:36 PM UTC 24 47585944 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3844532903 Aug 27 07:44:13 PM UTC 24 Aug 27 07:44:37 PM UTC 24 8997446618 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3314253313 Aug 27 07:44:23 PM UTC 24 Aug 27 07:44:38 PM UTC 24 5997190170 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.3005887917 Aug 27 07:44:36 PM UTC 24 Aug 27 07:44:38 PM UTC 24 16080835 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3904008266 Aug 27 07:44:08 PM UTC 24 Aug 27 07:44:40 PM UTC 24 1317646990 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1182490693 Aug 27 07:44:38 PM UTC 24 Aug 27 07:44:40 PM UTC 24 27650505 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1374576295 Aug 27 07:44:36 PM UTC 24 Aug 27 07:44:42 PM UTC 24 6769274836 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1029489074 Aug 27 07:44:39 PM UTC 24 Aug 27 07:44:43 PM UTC 24 1602011879 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.4081645926 Aug 27 07:44:26 PM UTC 24 Aug 27 07:44:44 PM UTC 24 4416832557 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2382942972 Aug 27 07:44:39 PM UTC 24 Aug 27 07:44:48 PM UTC 24 566962078 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1183756830 Aug 27 07:43:47 PM UTC 24 Aug 27 07:44:48 PM UTC 24 7677618303 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.887522021 Aug 27 07:44:19 PM UTC 24 Aug 27 07:44:49 PM UTC 24 2982132181 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.3506981241 Aug 27 07:43:47 PM UTC 24 Aug 27 07:44:51 PM UTC 24 3781592616 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.4113928078 Aug 27 07:44:45 PM UTC 24 Aug 27 07:44:54 PM UTC 24 374878318 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.2766455128 Aug 27 07:44:37 PM UTC 24 Aug 27 07:44:55 PM UTC 24 2462353913 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1049850274 Aug 27 07:44:49 PM UTC 24 Aug 27 07:44:57 PM UTC 24 793629908 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.3804202674 Aug 27 07:44:56 PM UTC 24 Aug 27 07:44:59 PM UTC 24 42363449 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.4131352541 Aug 27 07:44:58 PM UTC 24 Aug 27 07:45:00 PM UTC 24 23873891 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.2715388601 Aug 27 07:45:00 PM UTC 24 Aug 27 07:45:02 PM UTC 24 54025690 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.982160447 Aug 27 07:42:44 PM UTC 24 Aug 27 07:45:04 PM UTC 24 10259010725 ps
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